Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Industry News | 2003-01-27 10:27:31.0
At a New Facility Within the Company's U.S. Headquarters
Industry News | 2005-09-19 16:07:56.0
No higher temperature and No process changes needed
Industry News | 2003-02-17 08:40:25.0
To Meet Government Environmental Standards and Individual Company Policies, While Satisfying Production Requirements
Industry News | 2008-02-28 21:48:17.0
OXFORD, CT � February 2008 � MIRTEC a leading global supplier of AOI systems to the electronics manufacturing industry, announces that it will introduce its MV series of AOI systems in booth 1857 at the upcoming APEX exhibition & conference scheduled to take place April 1-3, 2008 in Las Vegas.
Industry News | 2015-06-11 16:02:18.0
MIRTEC, "The Global Leader in Inspection Technology," will exhibit its most recent solutions for System in Package (SiP) inspection and measurement at SEMICON WEST 2015; July 14-16, 2015, at the Moscone Center in San Francisco, CA. Visitors are invited to booth # 2343 for a detailed demonstration of this exciting new technology.
Industry News | 2003-06-10 08:16:44.0
The following text describes the application of NWA Quality Analyst to quality control in the assembly of electronic components.
Industry News | 2009-03-16 18:07:28.0
OXFORD, CT � March 2009 � MIRTEC, �The Global Leader in Inspection Technology,� announces that it will introduce the latest advancements to its MV Series of AOI systems as well as unveil the company's first In-Line SPI System, the MIRTEC MS-11, in booth 147 at the upcoming APEX exhibition & conference scheduled to take place March 31- April 2, 2009 in Las Vegas.
Industry News | 2012-01-23 00:02:12.0
MIRTEC, “The Global Leader in Inspection Technology”, will premier its complete line of 3D AOI, SPI, X-ray and LED inspection systems at the IPC APEX Expo in booth #3637.
