Full Site - : tenting via (Page 13 of 16)

Re: Providing Thermal Relief On Vias

Electronics Forum | Wed Jun 03 21:25:33 EDT 1998 | John Allan

| Hello: | BACKGROUD: SMT components soldered on the top-side of boards that also require wave soldering have the potential to reflow during wave soldering. Reflowing these components during wave soldering is not good. It can cause cold joints, op

Re: Shorts on BGA

Electronics Forum | Mon Mar 15 09:55:53 EST 1999 | Justin Medernach

| After rmoving a BGA (plastic)to correct unexplained shorts | I installed another BGA using flux only. | Checking on an X Ray machine and found two shorts. | | can anyone give a good explenation ? | | Thanks | | Ron | Ron, It could be a number o

Re: Via Sizes

Electronics Forum | Thu Nov 25 21:43:49 EST 1999 | cklau

Via is normally a plated thru holes in (0.63 to 1.0 mm (0.025" to 0.040") diameter lands , which unless properly treated they must be located away from the component lands to prevent the solder migration off the component land during reflow soldering

Re: Need advise on regarding Vias

Electronics Forum | Tue Dec 14 01:05:09 EST 1999 | cklau

Hi All I have a 0.7 mm diameter hole for vias, what�s the minimum annular ring for this hole diameter? Ans: Fur inner layers Min = .006" hole-pad annular ring ; inner pad dia - hole dia/2 For outer layers Min = .005" hole-pad annular ring ; outer p

how to prenvent flux risidue in the blind vias.

Electronics Forum | Mon Feb 19 22:56:20 EST 2007 | davef

Russ We agree with your comments on plugging from one side only. But... We believe that it IS possible to trap process chemicals [technically, not flux] in a blind [or any other] via. This can be done by plating the via closed, rather than pluggi

Question about solder masking BGA vias...

Electronics Forum | Mon Sep 20 13:04:25 EDT 2004 | davef

The Intel BGA Developer�s Guide [ http://developer.intel.com/design/packtech/ch_14.pdf ] says: 14.8.3.3 Plated Through Hole (PTH) Isolation Regardless of the technique used for the mounting pads shape or definition, isolation of the plated through h

QFN PCB Pad no Drain Hole

Electronics Forum | Sat May 18 15:19:55 EDT 2013 | isd_jwendell

OK, I've now read all of the documents you referenced. The problem still remains regarding the thermal vias and how to minimize scavenging. All the docs acknowledge top and bottom tenting, and it's problems. TI says don't do it. Plugging is usually n

Re: Plating crack

Electronics Forum | Wed Sep 27 19:37:32 EDT 2000 | Dave F

Wolfgang is correct. Copper plating thickness of the via barrel walls is a key question you need to answer to troubleshoot this. Tenting is a red herring.

Re: Providing Thermal Relief On Vias

Electronics Forum | Thu Jun 04 12:22:12 EDT 1998 | John Allan

| | | Hello: | | | BACKGROUD: SMT components soldered on the top-side of boards that also require wave soldering have the potential to reflow during wave soldering. Reflowing these components during wave soldering is not good. It can cause cold jo

Brd(Electroylic Gold finishing) got blisters

Electronics Forum | Wed Aug 24 21:57:45 EDT 2005 | adeline_ko

The blistering is around the plugging via. I can forward you the pic. For the plugging process, I'm not too sure how they plug. What is the correct practise for the plugging via. Now, what they did is. They will do a tenting process for both side.


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