New Equipment | Solder Materials
Indium Corporation manufactures high quality solder powders and pastes. Powders are available in hundreds of alloys and a full range of sizes. Solder pastes can be made from these powders using a wide variety of flux vehicles to get the best fit for
Industry News | 2016-09-01 19:24:28.0
KIC today announced that Marybeth (MB) Allen will present “Optimized Reflow Profiling to Minimize Voiding” during SMTA International. The presentation is scheduled to take place during the IPC Session ‘Lead-Free Symposium,’ Session LF2 on Thursday, Sept. 29, 2016 from 11 a.m.-12 p.m.
Technical Library | 2011-04-07 14:50:29.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry nowadays. This package offers a number of benefits including (1) small size, such as a near die-sized footprint, thin profile, and light weight; (2) easy PCB t
Industry News | 2016-04-21 19:00:55.0
Indium Corporation's Brook Sandy-Smith, Technical Support Engineer for PCB Assembly Materials, will present at the International Conference on Soldering and Reliability (ICSR) 2016 on May 9-11 in Toronto, Canada. Sandy-Smith will present How Stencil Design and Reflow Profiles Affect Variation in QFN Voiding Data: A Case Study. This presentation will include data from several studies that demonstrate how stencil design and reflow profile optimization impacts voiding levels and variation in material comparison testing.
Industry News | 2007-10-23 17:27:36.0
Indium Corporation�s *Indium5.1AT Pb-Free Solder Paste *is an Award-Winning No-Clean, Pb-Free Solder Paste that delivers enhanced finished goods reliability by featuring;
Technical Library | 2023-01-17 17:16:43.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Industry News | 2019-01-04 16:11:03.0
KIC will exhibit in Booth #1215 at the 2019 IPC APEX EXPO, scheduled to take place January 29-31, 2019 at the San Diego Convention Center in CA. Visit the KIC booth for a reflow profiling clinic for void reduction.
Industry News | 2022-05-05 17:38:12.0
The Assembly Division of MacDermid Alpha Electronics Solutions, a global supplier of integrated solutions from our Circuitry, Assembly and Semiconductor divisions that provides unmatched capabilities in electronics design and manufacturing will discuss solutions for voiding at the SMTA Juarez Expo & Tech Forum on Thursday, May 19.
Technical Library | 2018-09-26 20:33:26.0
Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and – most notably – center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation. Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.
Technical Library | 2024-07-24 01:04:35.0
Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.
