Electronics Forum: 003 (Page 3 of 13)

J-STD-003

Electronics Forum | Fri Feb 15 16:56:46 EST 2013 | davef

I'll throw my hat in the ring that says, "At least 95% of the pads must be properly wetted." BR, davef

J-STD-003 - All Must Be 95% Or Better

Electronics Forum | Wed Feb 20 12:44:21 EST 2013 | davef

From IPC APEX ... Hege is correct ... ALL pads have to be 95% wettable or better. BR, davef

J-STD-003 - All Must Be 95% Or Better

Electronics Forum | Mon Feb 25 15:14:42 EST 2013 | bmario

Thank you guys! I will use this interpretation. However it is hard to meet when using the wave method.

J-STD-002 and -003 solderability testing...

Electronics Forum | Fri Jun 29 14:15:00 EDT 2001 | stefo

This is a question about complying with J-STD-001 solderability testing. Do any of you have your vendors certify that the components and PCB's that you buy from them comply with the solderabilty requirements spelled out in the -002 and -003, in lieu

Re: Calculate SMD movement during reflow?

Electronics Forum | Wed Nov 03 20:02:44 EST 1999 | Anthony Winston

Well John here is the situation: I need to place an infrared transistor (optical element) with a tolerance of +/-.003", this is not a problem. A lens is positioned over the optical element and snapped to the PCB via three holes that have a toleran

Qualification requirements for immersion tin finish

Electronics Forum | Wed Aug 30 08:20:40 EDT 2006 | Bob R.

Are there any standard qualification/acceptance requirements for immersion tin board finish? J-STD-003 calls out temp/humidity preconditioning followed by solderability testing which is similar to what we have in our (ancient) internal documents. O

Minimum Tg for LeadFree board.

Electronics Forum | Fri Aug 21 00:27:09 EDT 2009 | boardhouse

Hi To Start Min Tg is just a portion of picking a lead free material, the other is Td. We recommend the following to our Customers. 2-8 layer 150 Tg. Min. / 340 Td. 8-Up. 170-180 Tg.Min. / 340 Td. The above recommendations have been used by man

General ROI (Return on Investment)

Electronics Forum | Mon Jun 11 17:14:13 EDT 2012 | mmjm_1099

1st Question I am working on ROI for a bare board destacker and wondering if anyone has a general guideline to follow. Example of ROI for bare board destacker I have now as follows: $7500 for destacker, Avg panel input 3365, Time to load in panel 7

component attrition

Electronics Forum | Tue Feb 06 10:55:58 EST 2001 | pjc

Larry, Our specification is 0.075% for our Fuji CP3 and IP2 machines. At or above that figure the Maintenance Dept. has to get to work. We typically see 0.03% to 0.05% on average. The Fuji machines are all vision centering. We have found feeders are

Contamination of components

Electronics Forum | Sat Mar 03 23:24:55 EST 2001 | CAL

We test Parts and Components to IPC J-std-002/003. We also use a wetting Balance tester to determine solderability. We also test with SERA. We use ROSA to electrochemically revert the components back to their original state. Need more info ... email


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