Electronics Forum: 20.00 (Page 5 of 11)

Ionograph calibration tables?

Electronics Forum | Thu Dec 14 20:00:03 EST 2023 | stephendo

I would think that it would be the readings you get from known calibrated samples. i.e. you get samples to test with known values and you test them and see if you get the correct values. Don't rule out your customer not knowing what they are asking

Re: Component Package Specs

Electronics Forum | Wed Jan 12 14:43:54 EST 2000 | JAX

Doug, Jedec has this info. Here is a few for you to use. LENGTH, L+LEADS, WIDTH, W+LEADS, PITCH, AVG. HEIGHT. 1. CQFP100AC: 17.28,22.35,17.28,22.35,.635,4.92 2. CQFP100AF: 32.52,37.59,32.52,37.59,1.27,4.92 3. PQFP100AD: 19.05,22.35,19.05,22.35,.

Re: flashing LEDs circuit

Electronics Forum | Mon Apr 20 00:19:20 EDT 1998 | Marcos Silva

Ola Pelegrini, Trabalho em Sao Paulo, na Siemens. Sou respons�vel pela assistencia tecnica de maquinas insersoras SMD. Acredito que possa consultar nossa divisao de componentes - ICOTRON, a fim de consultar sobre este componente. Nosso telefone: 011-

Re: Open v.s viscosity

Electronics Forum | Thu Apr 20 00:53:23 EDT 2000 | Wister

Hi,Dave The "skip" wouldn't happened because we monitor the solder paste height every two hours.The open position is between chip terminal and the solder paste.one terminal lift a little not as same as tombstone.I suspect the activity of solder paste

Stencil Cleaning OnBoard Forum Now In Progress

Electronics Forum | Wed Feb 21 20:00:09 EST 2001 | davef

Sounds like you received some good advice. Most of our stencils are used once a day [at most], so more often than not they are air dried. If we goof-up and need to reuse a stencil during a day when we have limited drying capacity, we wipe the lowes

Question on BGA Solderability

Electronics Forum | Tue Jul 24 20:00:40 EDT 2001 | davef

There is too little heat to make the solder flow properly. Test this theory by profiling on the pad where the solder doesn�t flow well. As the time after posting this thread increases, we generally propose additional theories. Rather than us specu

solder crack

Electronics Forum | Sun Jun 30 20:00:56 EDT 2002 | redmary

the SOIC encounter solder crack after reliability test, the common process is: SMT---manual soldering---IPT(in process test)---potting---T/C(thermal cycling,only add current and voltage)---B/T and F/T (burn in and functional test). the condition is 2

PBGA Replacement

Electronics Forum | Mon Sep 22 16:00:43 EDT 2003 | Joe

Two BGA replacements (same location) and throw the card away is the rule we are following. Experience has taught us that anything beyond this and you'd be pushing it - specifically when your new PBGA's price is above $20.00. The biggest concern is

Conformal coating application

Electronics Forum | Mon Sep 27 20:00:24 EDT 2004 | davef

We agree with Hoss. Dipping is far more controllable and less expensive than spraying for the casual user. An alternative to consider contracting your coating requirements. Amoung the service providers are: * http://www.newenglandcoating.net * htt

Drop components in Secon reflow

Electronics Forum | Thu Aug 25 20:00:31 EDT 2005 | Dave

Try Heller Industrie's website at http://www.hellerindustries.com They have a formula that they offer for free that calculates land pad geometry to component weight to prevent drop off of components during second reflow. If you can't find it, give t


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