Electronics Forum | Tue Nov 21 22:15:59 EST 2000 | Vince Whipple
Mohammed, The first suggested place to start with your question would probably be with your flux Mfr. Push them! The quantity of dross is effected by several factors: The higher your solder pot temp., the higher your dross level... but don't go too
Electronics Forum | Fri May 21 15:20:26 EDT 1999 | JohnW
| I normally handle the soldering issues for this facility but a question was asked of me -- What the H@## is this stuff and what is causing it? Was wondering of I could get some input from any Guru on plating issues. Need info ASAP!!!!!!!!!!!!!!!!!
Electronics Forum | Mon Jun 28 10:03:22 EDT 2004 | davef
First, welcome to your new job. Second, IPC-TM-650 2.6.14 is only loosely an �Ionic Contamination (Electromigration) Test�. * Electromigration Test, IPC TM 650 2.6.14, 2.6.14.1 * Ion Chromatography for Ionic Cleanliness, IPC TM 650 2.3.28 Third, I
Electronics Forum | Sat Apr 25 12:58:13 EDT 1998 | Earl Moon
| Is there an industry standard in calculating SMT process | PPM level for benchmarking purpose ? What are the industry | benchmark ppm number for some of the defects like solder | short for 20-mil QFP, tomstone problem for 0603 components etc....
Electronics Forum | Mon Oct 21 13:40:05 EDT 2002 | slthomas
Is it safe to use the 100M ohm value found in Table 2 of J-STD-004 as a minimum for SIR with respect to flux specification acceptability? It (J4) appears to imply that that value provides some level of acceptability, but it just doesn't come right o
Electronics Forum | Thu Feb 23 10:49:38 EST 2006 | slthomas
Defining failure modes will help determine what you need to quantify in all processes. Personally I wouldn't pursue the DoE angle (varying setup parameters to determine robustness). 1)How about % pad coverage, paste thickness, and accuracy? Define w
Electronics Forum | Thu Aug 09 09:05:09 EDT 2007 | davef
There are no requirements acceptance criteria for baking of board assemblies. What are your customer requirements? The common reasons people choose to bake PCB are to prevent: * Delamination of multilayer boards * Measles, particularly on double si
Electronics Forum | Sat Nov 08 09:10:16 EST 2008 | davef
SN100 was designed for selective soldering and producing low levels of voiding. But thin barrel plating is a common cause of voids in wave and selective soldered connections, as you say. As a result, you checked the plating thickness and it was accep
Electronics Forum | Wed Oct 19 07:04:06 EDT 2022 | winston_one
If any changes in design is not possible and you have to solder it, it's a real headache, I know... I see only 3 options here that you can try consiquently: 1) Accurately profile the board and optimize a profile (go to lower limit of process windo
Electronics Forum | Tue Sep 05 07:38:36 EDT 2000 | JAX
Daniel, I think JOHN and Ramot have some good ideas but I guess I am a little confused. How have you placed BGA's or QFP's in the past. If you are just starting to place them and believe you will continue to in the future, you need to start looki
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