Electronics Forum: acceptable chloride levels (Page 10 of 25)

What is the QFN or Device Voiding Levels Needed for Automotive Industry for Power Devices for Electric Vehicles?

Electronics Forum | Thu Mar 16 03:45:51 EDT 2017 | rob

It's the same thermal issue whether it's a die or package. It's different if it is just a signal trace, but if it's a heatsink pad (LED, FET, Motor driver, PSU IC etc). I think the voiding issue boils down to what the part is actually doing. The or

Bridge Defects

Electronics Forum | Fri Jun 30 14:13:23 EDT 2023 | calebcsmt

Is a bridge considered a defect, if adjacent pads/component leads are electrically connected (common) via a trace but said trace is covered in solder mask ? Essentially, of course bridges are never a target but is rework required/de-bridging require

Inspection Equipment

Electronics Forum | Thu Sep 27 11:59:14 EDT 2001 | vance

Programming time is going to be your biggest concern with a high mix environment. This includes maintaining programs. Any time a part's appearance changes (color, location of marking, wording, etc) templates need to be modified in some way to produ

Water Quality Requirements to wash boards

Electronics Forum | Mon Apr 15 22:08:41 EDT 2002 | ianchan

Dave F, Hi Expert, You are too modest, if anyone can qualify as expert so far, its you...(silent homage to the other unsung experts). Coming back to "FIX", apologizes, meant to term it "fix" as in "established specifications". and yep, seems the fo

Throw out component from - placement machine

Electronics Forum | Thu Jul 20 19:51:40 EDT 2006 | darby

Are you trying to tie someone to an agreed wastage level or are you being tied? What machines are you talking about? What components are you talking about? The only acceptable wastage level is zero: but you can't get to zero until you've had some was

Dual Process for Reflow

Electronics Forum | Fri Aug 01 10:24:04 EDT 2008 | edmaya33

Hello Reflow Masters; I'm using an Omniflo-10E reflow oven. Due to high demands of our production in lead free process, can I use my existing leaded line as an native? Does this option affect the lead contamination of the solder in Pb-Free to go bey

Wave Solder DPMO Target

Electronics Forum | Fri Apr 06 17:06:43 EDT 2012 | joeherz

Hello, We have been tracking our SMT quality levels using DPMO which has been a great way to monitor our process with a huge variation in products we build (we're an low vol/high mix EMS provider). We are now looking at implementing the same scheme

Any comments for Quality @ AQL=0.1, C=0 ???

Electronics Forum | Mon Mar 25 15:51:04 EST 2002 | davef

ASQC re-numbered the once free (taxpayer sponsored development) MIL-STD-105 as ASQ-Z1.4, slapped their own cover on it, and now charge $40 or $50 for the same document! The standards are identical, so see if you can get one of the old �MIL-STD's� and

Re: Design Guides

Electronics Forum | Wed Jul 22 12:47:23 EDT 1998 | Earl Moon

| I'm trying to put together a set of design guides for use for new designers | in house or to be sent out for contracted layout work. I would like to start with a top ten list of things that will go wrong if rules aren't available. For example testp

Re: haloing on SMT PCBs

Electronics Forum | Mon Jun 08 15:01:02 EDT 1998 | D.Lange

| I work QA at an OEM in Alberta, Canada. I saw earlier posts on the smtnet regarding PCB haloing criteria. I am currently in a dispute with my PCB vendor over the acceptability of haloing (delamination) around plated through holes and vias on a lot


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