Electronics Forum | Thu Jan 29 09:29:42 EST 2015 | rgduval
In general, it depends on what you're working on. Boards with a higher thermal profile might require higher temps. But...the usual answer is...set your irons to the lowest temperature possible that still achieves the goal. We usually keep our ir
Electronics Forum | Fri Feb 19 15:23:31 EST 2016 | ttheis
RESOLVED I adjusted the "Minimum Board Width" in the Board Handling Configuration to resolve this issue. I set the lane width to a larger value which did not hit the front limit and measured the difference between the actual lane width and the set l
Electronics Forum | Wed Mar 15 12:39:24 EDT 2017 | cyber_wolf
Customer precedes standard, but customer must be educated and informed on what is achievable with their design and what is accepted as industry standard practice. My guess is that the negative effect of those voids is negligible. {Voids at the sold
Electronics Forum | Tue Jul 25 09:30:08 EDT 2017 | cyber_wolf
"We use Mistral 360 with glass top where you can "see" your process while board pass through the oven, you see when the paste dry, you see when the reflow starts, what is the time above liquid etc etc, and can adjust up or down with few degrees in ea
Electronics Forum | Thu Dec 14 04:42:11 EST 2017 | jineshjpr
Can anybody suggest how can I achieve good solderability in convectional reflow oven If I reduced Convection Air Speed 80%. The whole purpose is to reduce 0402 LED tilting in the convectional reflow and the PCB having QFN with 60 to 120 sec soak, 30
Electronics Forum | Wed Sep 12 03:52:45 EDT 2018 | shascoet29
Hi, Is the IPC-A-610 applicable to CSP assemblies? Especially regarding the solder ball to solder ball distance versus the minimum electrical clearance for assembly(0.13mm/IPC-A-610). With a 0.4mm pitch component and 260 microns diameters balls, thi
Electronics Forum | Wed May 22 06:05:28 EDT 2019 | sarason
UFOS is a much earlier format which has very truncated details over VIOS , so as an intermediate going from later formats such as the versions of VIOS you are suggesting, is probably not the best, or more succintly it sucks. Send me a copy of your in
Electronics Forum | Tue Jun 11 08:09:36 EDT 2019 | smith88
Per IPC and Jstd CC should cover all required areas but it is acceptable to have voids and other anomalies as long as they do not bridge exposed conductors. Am I interpreting it correctly if the drawing states assemble per IPC it has hatched areas. S
Electronics Forum | Tue Jul 30 05:26:46 EDT 2019 | ameenullakhan
thanks dave .. I have one more query on the same CCGA. What are the chances of the CCGA lead getting bent or tilt during reflow soldering process. Concern : to achieve the minimum peak temperature of 208 deg C at the connecting leads. On bod
Electronics Forum | Wed Oct 23 10:22:55 EDT 2019 | maxwilko
Hey Kathy, Thank you for the link for the tech support will keep that in mind for the future! After a long series of testing different solutions we found that re-sending the Gerber data over to the 'My500' seems to have resolved the issue, we are n
