Electronics Forum: ausn (Page 2 of 4)

Substrate Au/Ni thickness

Electronics Forum | Mon Feb 19 18:57:49 EST 2001 | davef

Expanding on the limit of the portion of gold acceptable in a solder connection [mentioned in an earlier post]: The embrittlement culprit, AuSn4, is 29 weight percent gold. So even if one had 100% tin as the solder alloy and 10% gold were dissolved

lid soldering problems (CQFP, Au/Sn solder)

Electronics Forum | Thu Sep 17 07:06:15 EDT 1998 | joakim fagerlund

We have problems with voids when we solder lids to ceramic flatpackages. The sealring of the package is gold(100 micro inches or 2.5 micro meters)with a underlayer of Nickel The solder is attached to the lid (preform) and the solder material is Au/S

Problems with TI DSP modules

Electronics Forum | Thu Oct 25 16:48:29 EDT 2001 | Cemal Basaran

We can inspect and measure strain field in anything larger than 320nm with Laser techniques we have. We can do this measurements during fatigue testing. Of course thick intermetallic region as a solid region is a problem due to the fact that you ha

Voiding Control on AuSn preform reflow process

Electronics Forum | Wed Apr 05 11:55:28 EDT 2006 | Cristina Oanca

I am working on a Substrate attach process. The package is gold plated, the preform is AuSn and the backing on the substrate is PdAg. I am using a Sikama reflow furnace. The profile has a 50 sec dwell time. I am over 280 degees C for a little over 1

solder SnPb wire to gold plated IC

Electronics Forum | Sat Apr 14 09:28:58 EDT 2007 | davef

When soldering a component to a board, the solderability protection on the component combines with the solderability protection on the board and the solder to form an alloy. This alloy is unique for that combination of solder and solderability protec

80/20 Au/Sn Solder and Proper FLux Selection

Electronics Forum | Mon Jan 17 17:38:29 EST 2011 | bandjwet

All: I am reaching out to get some suggestions on the right flux to use as well as a recommended cleaning process for soldering a KOVAR RF shield using 80/20 Au/Sn solder to a ceramic hybrid. The recommended profile is 4-5 min at 280C and at least

PTH Voiding Caused by Gold Plated Leads

Electronics Forum | Tue May 21 16:18:57 EDT 2019 | edhare

Interesting problem. I've seen this before on SMT device leads (see Gold Embrittlement paper at http://www.semlab.com). The AuSn4 IMC is solid at typical reflow temperatures and traps volatiles in the solder joint. One usually cannot crank the ref

Gold Surface Finish on PCB's

Electronics Forum | Thu Dec 08 07:55:16 EST 2005 | davef

Your understanding of the situation is correct. In both cases, you solder to the nickel. The gold [Au] protects the nickel from oxidation. When soldering, the gold moves into solution in the solder and forms an intermetallic compound [IMC] with th

Dull joints caused by NiAu PCB surface ?

Electronics Forum | Thu Nov 01 17:40:52 EST 2001 | davef

Listen to Wolfgang. Your dull solder connection is a process indicator. Some 63Sn / Au solder connections look grainy, depending on how your process them and the materials involved. Gold dissolving in tin forms an intermetallic compound [AuSn4] th

Lead Free solder

Electronics Forum | Sat Nov 21 12:28:00 EST 2009 | flipit

There is evidence of lead being used in soldering 5000 years ago in Mesopotamia. Not a big issue for most people doing SMT but the poster should also understand why percent metal is adjusted for different solder paste alloys. You print by volume b


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