Electronics Forum | Wed Aug 18 16:15:04 EDT 1999 | Earl Moon
| Hadco offers a technology of building in a "buried" capacitance layer (& other embedded passives) in organic PWBs (FR4 for example). see http://www.hadco.com/prod03.htm and a design manual is posted here: http://www.hadco.com/pdfs/bcguide.pdf | I
Electronics Forum | Wed Sep 01 14:07:41 EDT 1999 | Dave F
| For space contracts we have to mount chip capacitors/ resistors etc 0.1 to 0.4 mm from the pad height. | | This is to compenstae for the CTE differential in the substrate/component and also to ensure cleanliness. | | Does anyone have any new idea
Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F
=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so
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