Electronics Forum | Tue Mar 05 11:08:31 EST 2019 | mrk
Hi all, We have an assembly which features non-plated tooling holes used to align the board in a bed of nails style test fixture. This assembly is rather small, and as such, the test points are pretty small as well. We have found that some variation
Electronics Forum | Wed Feb 12 16:48:31 EST 2014 | gmcquoid
We are having an internal debate here related to minimum Conductor Width. Can you have your QA manager review this and advise. IPC-6012C-2010 3.5.1 Conductor Width and Thickness When not specified on the master drawing the minimum conductor width s
Electronics Forum | Tue Nov 09 05:14:49 EST 1999 | Wolfgang Busko
Hi all, our problem we face is the mismatch of conductor width on the delivered PCB and the nominal width given by CAD-data. With CAD we are improving pads and conductors to match the specific needs for soldering and the board houses counteract our i
Electronics Forum | Tue Nov 09 11:32:32 EST 1999 | Dave F
Wolfgang: "Our desire is to get what we design" ... Wanting to get what you ask for ... ummm sounds like a risky proposition!!! ;-) Two things: 1 Go to the Hadco site and get their "boiler-plate." Use it and some of the Earl Moon specs in the SMTn
Electronics Forum | Thu Apr 15 05:17:51 EDT 1999 | Barry Aylett
Can anyone suggest or identifiy standards which tabulate the following: Conductor width, cross sectional and area conductor thickness for PCB's carrying up to 70 Amps?
Electronics Forum | Tue Nov 23 08:53:22 EST 2004 | russ
I believe that a conductor is a conductor regardless of type, so the surface finish counts. What are the pad spacings that you speak of?
Electronics Forum | Mon Jun 24 22:39:25 EDT 2019 | sssamw
yes, the void should not expose the conductor or bridge the conductor, the coating there should be thick as IPC required but you need minimize the voids and bubbles. ALso for those small chips, a void or bubble on it means possible ECM, normlly shou
Electronics Forum | Tue Nov 28 17:23:03 EST 2006 | flipit
Flash gold usually refers to electrolytic gold with a short plating time. In other words gold plating that requires current to plate. If you have bare copper under your soldermask, the gold is probably ENIG. The only other way to have bare copper
Electronics Forum | Wed Mar 03 09:05:28 EST 2004 | davef
Look to IPC-2221, 9.1.3 Thermal Relief In Conductor Planes
Electronics Forum | Thu Feb 08 08:20:52 EST 2007 | mzaboogie
tjc, Is this pin connected to a heavy conductor or ground plane? Chris
