Electronics Forum | Tue Dec 23 11:10:15 EST 2003 | dougt
Alright this guy's promising the world. If anyone uses this company as a result of this thread please let us know if your able to get 0805's, 0402's or 0201's that you couldn't get anywhere else. We don't have size constraints and have been using 12
Electronics Forum | Mon Sep 26 01:44:51 EDT 2005 | vinc
Just be aware of what Japanese had done. They do not stick to one alloy as it is impossible and depends on the constraint you are facing with. As for Hitachi, according to one advertisment put up in SMT magazine seems to me that they are going for
Electronics Forum | Mon Apr 11 06:37:59 EDT 2005 | amstech
As long as you have a continuous profile with required soak and dwell periods, the zone lengths do not matter. For lead free, usually ramp to peak is preffered.that is with minimum soak (you can not avoid soak anyway. You can achieve the profiles irr
Electronics Forum | Thu Jul 14 13:05:18 EDT 2005 | Bman
Considering all the constraints you are faced with, I would try changing the apatures for that part on the stencil. It seems as though a no-clean "homeplate" appature would put less paste on the board. Less paste means less flux, and it might be en
Electronics Forum | Fri Jul 15 13:16:08 EDT 2005 | Brian
We have seen this problem in the past and had to deal with similar customer constraints. It's not the flux causing the wetting, but the placement and pad geometries as some have mentioned. To reduce or eliminate the problem, we have changed the ape
Electronics Forum | Wed Nov 16 10:36:30 EST 2005 | B. Tamland
Has anybody had to wave solder components after PEM hardware has been installed to the wave side of the board? Design constraints on the product force us to do this, and we need to determine a method to mask the PEM's. Anybody try hi-temp boots / C
Electronics Forum | Wed Nov 16 11:30:20 EST 2005 | nkbkiran
If PCB board size is my constraint ....and I have designed my circuit ... 1. How to optimize the layout of design for smaller space? 2. How to run simulations if any to do intelligent SI test? Does packages by Cadence, Mentor support this kind of o
Electronics Forum | Tue Feb 13 14:33:16 EST 2007 | CK the Flip
So the moral of the story is..... these SAC305 BGA's were accidentally mixed in with a Leaded process, the profile couldn't get hot enough due to Tg and Td constraints on a known good QFP on the same board, and consequently, the whole assembly fail
Electronics Forum | Mon Sep 24 12:47:37 EDT 2007 | PJ
I am doing some research on flux free/flux less SMT reflow soldering. Do you have any equipent/process recommendations? Does anybody use it for volume production and what are the constraints (finish, balls, paste, vacuum, pressure, size)? What is
Electronics Forum | Thu Jun 19 12:07:09 EDT 2008 | ck_the_flip
You answered your own question! Vapour phase is the way to go for this. Conventional ovens won't allow this, unless you find away to defy Physics. That's an absurd constraint to begin with: 200C. Most Sn-Pb profiles require 205 - 210 minimum for
