Electronics Forum: defect (Page 19 of 226)

No-Lead solder defect - No solder on pads

Electronics Forum | Mon Dec 22 19:43:43 EST 2003 | Dean

I have seen this affect on Immersion Tin and OSP. 70 to 90 % of the solder wicks to the lead and forms a "single" homogenous solder mass. This even though the pad was 100 % covered with paste... Evaluated different solder paste...did find variatio

No-Lead solder defect - No solder on pads

Electronics Forum | Tue Dec 23 19:27:01 EST 2003 | davef

A more active flux may help, but if the nickel underplate on the component body is corroded [and not soldering], if could require a VERY active flux. Just an off-the-wall thought, are you sure that your heat recipe activates the flux properly? Slow

What defect in SMT will be cuased by dust contamination?

Electronics Forum | Tue Mar 09 20:58:48 EST 2021 | emeto

This have been solved by storing the boards right in all places I have worked. You open a pack, label and use. If you collect dust in such a small time window, you should totally start paying for cleaning service of the building. Electronics we build

What defect in SMT will be cuased by dust contamination?

Electronics Forum | Thu Oct 21 13:08:38 EDT 2021 | ademrah

Hi, It depends on smallest pitch size of your components. For the 0.3 um, 0.5 um, etc. sizes could be mentioned on Clean Room. For example; for ISO-7 standart (Class 10,000) higher than 5um is not acceptable, however 1mm can acceptable to describ

No-Lead solder defect - No solder on pads

Electronics Forum | Mon Dec 22 15:35:18 EST 2003 | davef

Marc: Please be more explicit. * When you say, "parts have a metal shell"; are you talking about the component leads or the component body? What is the metal, what is it appearance, and what are it's implications? * When you say, "the parts have a

What is a typical SMT placement defect rate?

Electronics Forum | Thu Jul 10 15:03:57 EDT 2014 | alexeis

Hi, An answer to this question is very complex. The amount of components and their type is only one parameter to determine the level of failure. Additional parameters that can influence are: 1. The density components on the card 2. Machine type and

What is a typical SMT placement defect rate?

Electronics Forum | Wed Jul 16 11:57:11 EDT 2014 | markhoch

We're a Tier 1 Automotive Supplier building, what I like to call, Peanut Butter and Jelly Boards. (High Volume, Low Complexity) Our first pass yield, using standard 1st Article Inspection and AOI is about 98-99% on any given day. Last night, for ex

What is a typical SMT placement defect rate?

Electronics Forum | Mon Jul 21 12:23:31 EDT 2014 | jimmyboz

As has been pointed out by other well experienced individuals, this is a complex question. But the simple answer is "It is your decision". Choose any goal less than 100% and strive to reach it. There are hundreds of questions to ask before an obje

What is a typical SMT placement defect rate?

Electronics Forum | Sat Sep 27 19:41:55 EDT 2014 | cyle

In my office we strive for no retouch prior to reflow, it can be done, you just need your operator to be competent enough to know how to set up your machine correctly. I would say 99% of parts that are misaligned are user error, they are either not

Re: acceptable defect rates for smt process, in ppm.

Electronics Forum | Mon Jan 17 12:16:02 EST 2000 | Brian W.

My old company (CM) ran SMT to 50ppm including some very complex boards. We established the normalizer number by: #components + #solder joints. As was stated earlier, the ppm for any given product is the result of many factors. You may get differen


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