Electronics Forum | Wed Jul 03 15:58:16 EDT 2002 | davef
Your thinking is correct. Wave soldering pads that were designed for reflow can create problems: * Large pads used for reflow [too much solder] can create reliability problems. * Bridging [too much solder] creates rework. * Skipping & shadowing from
Electronics Forum | Wed Dec 06 21:28:12 EST 2006 | davef
It's worse than just using the test equipment manufacturer guidelines. Along with that, you have to deal with each of the test fixture fabricators' preferences as well. What this boils down to is a negotiation with the test engineering group as to w
Electronics Forum | Tue Jan 16 20:34:17 EST 2007 | davef
DAVE�S BOOKSHELF ASSEMBLER�S ESSENTIALS Title: Soldering in ElectronicsAuthor: RJ Klein WassinkPublisher: Electrochemical PublicationsISBN: 090115024XPublication date: December 1989 I know, I know. The book was written in 1989!!!! I use this b
Electronics Forum | Wed Feb 18 09:27:22 EST 1998 | SMT-ASSY
Good morning Larry, SMT-ASSY offers training for PTH and SMT soldering and rework, moreover we also offer training such as the SMT process (using production equipment such Vitronics oven etc.), Design for manufacturing, Design guidelines and other bl
Electronics Forum | Thu Feb 19 00:31:55 EST 1998 | Larry
The type of training I am looking for is things like micro BGA, flipchip, COB, new processes and techniques, ect. I already work with things like fine pitch QFP's, high mix double reflowed boards every day. I live in Vancouver, but I can drive to Sea
Electronics Forum | Sun Sep 05 03:52:11 EDT 1999 | Brian
| We've noticed that there are many different recommendations for pad sizes for various SMT parts. This seems to vary wildly from manufacturer to manufacturer for the same case sizes. Is there any standards that can used used to specify these sizes
Electronics Forum | Wed Oct 06 00:26:04 EDT 1999 | Karlin
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Wed Oct 06 08:41:42 EDT 1999 | Dave F
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Fri Oct 08 02:31:07 EDT 1999 | Brian
| | | | Hi, | | | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | | | Question: | | | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowab
Electronics Forum | Wed Oct 06 12:03:12 EDT 1999 | Graham Naisbitt
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
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