Electronics Forum | Tue Jul 20 06:36:50 EDT 1999 | Peter Brant
| Dear all | Please help me to know what kind of tests usually done after SMT Pick & place and reflow oven. | Our appliocation is Mainly fabrication of mother boards. | Thanks | Hi, The usual method is ATE, also known as a "Bed of nails" Basicall
Electronics Forum | Thu Jul 15 16:59:57 EDT 1999 | Glenn Robertson
| I'm designing a board where the parts will only fit if I do one of the following: | | 1. Put BGAs on both sides | | 2. Put BGAs on top, smt TSOPs directly underneath and using blind vias to keep the real estate on the bottom side below the BGA pa
Electronics Forum | Wed Jul 07 14:14:03 EDT 1999 | Dave F
| Is anyone aware of some guidelines regarding through-hole in SMT pads? One of our designers wants to add through-hole leads in some SMT pads for an inductor. The size of the hole is 0.032 inches and takes-up approximately 25% of the pad area. Th
Electronics Forum | Wed Jun 09 15:03:53 EDT 1999 | Earl Moon
| In past PCB designs I have cleared all traces from all layers | (except pwr/gnd) from fiducial area. It has come to my attention that this is only necessary on the side where fud is placed. Which is the correct method of design using a fidicial?
Electronics Forum | Sat Mar 06 08:35:21 EST 1999 | Dave F
| Clarissa, | | Dave had good suggestions. We load several boards manual at this time. We set our components up in clearly marked bins. The documentation includes a chart with the part number, bin number, reference designator and color code for t
Electronics Forum | Thu Feb 04 16:08:05 EST 1999 | Ryan Jennens
| I realize it's been discussed many times before. I need to know your opinions, experience, and knowledge concerning "today's"/latest and best pallet designs, suppliers, and methods for using them more effectively. | | Thanks much, | | Earl Moon |
Electronics Forum | Sat Jan 23 09:36:35 EST 1999 | Parvez Patel
Hi Everyone, We plan to build, for reliability/experimental/research purpose some CSPs (namely Tessera microBGA 46-I/O 0/75mm pitch and TI 64 I/O 0/8 mm pitch). the various factors that we plan to evaluate are the reliability and assembly concerns fo
Electronics Forum | Mon Dec 28 15:43:22 EST 1998 | Mark D.
We have a new PTH board that utilizes lap pads on the B/S. Some of the pads are paired closely together and are aligned at angles (30,45,60 degrees)to the boards direction of travel through the wave. The pads most always bridge together. I realize th
Electronics Forum | Mon Dec 28 19:28:57 EST 1998 | Chad Haima
| We have a new PTH board that utilizes lap pads on the B/S. Some of the pads are paired closely together and are aligned at angles (30,45,60 degrees)to the boards direction of travel through the wave. The pads most always bridge together. I realize
Electronics Forum | Mon Dec 28 08:19:58 EST 1998 | Earl Moon
| | Your question seems vague and very general. Gerber formatting is nothing more than describing points in an X-Y plane. It may be provided via CAD design capabilities or by manual means that has been digitized. Gerber data is "dumb" - meaning i
