Electronics Forum: every layer interconnect (Page 1 of 10)

GCpowerplace Inspection for Momentum Printer Bottom layer Issue

Electronics Forum | Tue Jan 15 10:08:19 EST 2019 | griinder

I'm looking for any experienced Graphicode software users for advice. We use Gerber EZ Teach(GC Powerplace) to offline program 2D inspection on our Momentum printers. I have an issue with mirrored apertures when creating my Bottom Side inspection pro

Inner Layer Separation from Barrel Wall - Too Much Heat?

Electronics Forum | Thu Nov 17 20:23:55 EST 2005 | davef

We're with your customer. We believe inner layer separation is not linked to a heating excursion. What you are seeing is separation between the hole wall and the copper plating in the barrel of the hole on an unstressed PTH. Although, it's possibl

Leakage resistance in PCB

Electronics Forum | Mon Feb 04 20:27:25 EST 2002 | davef

1,000 G ohm ||100 M ohm Dielectric Constant ||9.5 ||4.9 Loss Factor ||5 - 20 ||200 * E indicates exponent Continuing: * Spacing between same plane traces effect the electical parameters between the traces. * Dielectric materials used between diff

Re: Double sided reflow

Electronics Forum | Fri Apr 03 03:41:04 EST 1998 | Frank J. de Klein

150 secs. On bilayer boards (Cu only at top and bottom) you can typically not reach differences top to bottom bigger then 35-40 C. For multilayers however, the maximum is 15-20 C. If you actively cool a multi- layer at the bottom during the 2nd pass,

solder ball problem in manual soldering

Electronics Forum | Mon Oct 19 15:08:14 EDT 2009 | markhoch

Would be glad to offer some assistance, but I've got a couple of questions first: 1) What type of supplemental flux are you using? (If any) 2) Is your problem consistent across all assemblers, or can you trace the assemblies with solder ball issues b

Improving PTH fill using select solder

Electronics Forum | Tue Dec 18 10:14:14 EST 2012 | moshesh

In those cases where we have a 3.2mm thick, 16-layer board with several GND layers, do we still need ground connection to each and every layer (with thermal relief) or, skip part of the ground patterns? Will it help soldeing rising. I can't reach mor

Design dilemma

Electronics Forum | Thu Aug 23 11:19:40 EDT 2001 | Hussman

Hi delnosa, Sorry about being 10 days late - don't get to the bottom of the page much. I'm working of layering flex circuits sandwiched between FR4 layers. The flex is primarily designed to take the place of interconnects like yours. I work in ap

Thickness of layers en MLCC ?

Electronics Forum | Wed Sep 22 03:23:40 EDT 1999 | Jeanjean

Dear all, First, I'd like to thank every one of you who have been a great help for my last questions. Then, I have heard that in multilayer ceramic capacitors, each layer of ceramic was about 3 micrometers at least. When adding the layer (which I d

Re: Help I need DATA on Thermal shock caused by REWORK!

Electronics Forum | Sat Oct 02 03:27:52 EDT 1999 | Brian

| I am currently in the middle of a company wide war and I'm looking for data (AMMO). Here are the problems: | | 1) I am looking for anyone who has done or seen any reports on Thermal Shock to smt parts and/or via holes caused by Soldering Irons at

Re: Paste-in_hole and CTE

Electronics Forum | Fri Jul 28 14:34:13 EDT 2000 | Gary Simbulan

Belive it or not, these boards were run through a Centech batch mode Vapor Phase machine. Single stage top side IR preheat. Vapor temp 218 C. Solder paste is an SN62 RMA.The boards were FR4 8 layer w/ solder mask, fairly conventional as might be e

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