Electronics Forum: exposed copper vias (Page 1 of 29)

to seal exposed copper layers

Electronics Forum | Fri Oct 20 14:13:32 EDT 2000 | DENNIS XIONG

Dear all, We have a PCB design mistake that causes exposed copper layers on the edges of breakaway locations. Although we fixed the design, but we already made a lot of boards plus many made before we found the problem. I wonder if any one have some

Re: to seal exposed copper layers

Electronics Forum | Sat Oct 21 03:55:14 EDT 2000 | DL

Dennis, I've seen this before, and in our case we didn't need to seal the edges because there was no concern of shorting or anything in the end product, this is a choice you will have to make, Does your end product have any protrusions or mounting h

Tented vias on ENIG boards

Electronics Forum | Sun Feb 05 09:49:11 EST 2006 | Cmiller

We have been using ENIG for 8 years as our primary board finish. We have not seen any issues with tenting the vias. We have used a number of suppliers. The ENIG from China does not seem to solder quite as well in general but only had black pad from o

Tented vias on ENIG boards

Electronics Forum | Mon Feb 06 10:02:14 EST 2006 | Yash Sutariya

Sorry. I actually should clarify those slides. Black pad is not associated with tented vias. Also, you can tent vias with soldermask, but this requires the immersion gold process to be completed prior to soldermask. As such, all copper features (

PCB copper to disipate heat

Electronics Forum | Thu May 02 20:56:25 EDT 2002 | clunier

I remember reading a magazine article a few years ago that discused using the copper area of a pcb to transfer heat away from large SMT devices. Does anyone know of this article or something similar that I can obtain. The article covered copper area,

printing solder paste on test vias

Electronics Forum | Fri Aug 22 09:41:49 EDT 2003 | davef

Mantis: Kenny reflows paste on [wave solders] all via, not just the test via, to plug the via and provide for a pressure seal between the board and the test fixture. Beyond that, since solder is softer than copper [and fills the hole better], solde

piercing of test vias at ICT

Electronics Forum | Thu Nov 14 09:24:07 EST 2002 | joconnell

What about when debugging the board I recently saw a case where we damaged a board between - 5-10 cycles of the fixture It's a catch 22 - where you need high force probes to breal the OSP - but the copper is hard surface, not like the solder HASL a

via capping

Electronics Forum | Mon Jan 11 14:48:44 EST 2010 | davef

SR1000 is commonly used for tenting. Search the fine SMTnet Archives on : tenting Someone gave us this note. We have lost their name. It seems to be good advice. If Liquid Photo Image (LPI) solder mask is required, do not tent via holes. Tenting

Is This Corrosion?

Electronics Forum | Tue Jan 20 11:54:12 EST 2009 | smt_guy

Is this Corrosion? We found our boards with this issue 45 days after they were delivered to us from supplier. The board finish is HAL Leaded. But I noticed that the corrosion like issues are coming form the tiny via holes with SILVER EPOXY FILLING.

SMT with NO soldermask? selective plating...

Electronics Forum | Wed Aug 27 09:23:03 EDT 2003 | Darrow Gervais

I have an SMT application in which I would like to eliminate the soldermaks layer. I am working on a VERY tightly packed board so I cannot bury the traces and connected them to the pads with vias. I was thinking about selectively plating the expose

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