Electronics Forum | Thu Apr 17 18:18:34 EDT 2003 | davef
We undoubtedly will take you up on that offer. Please email contact information.
Electronics Forum | Mon Jul 07 11:40:32 EDT 2003 | davef
If it's soldering, you have good plating.
Electronics Forum | Thu Jul 10 11:23:36 EDT 2003 | slthomas
I think the guys that write the checks are convinced that it's a service, not a problem. :P
Electronics Forum | Mon Jul 14 17:20:06 EDT 2003 | davef
No cleanliness testing!!!! Yer just saying that to get a response, aren't you, Steve?
Electronics Forum | Wed Jul 16 17:12:50 EDT 2003 | davef
Massa be settin' yu freee, boi.
Electronics Forum | Fri Jul 18 08:42:12 EDT 2003 | iman
I can relate to your situation. You are not alone... good luck!
Electronics Forum | Thu Jan 12 13:21:11 EST 2006 | barryg
Opinions. I have a large finned heatsink that we place over a D2pak transistor. This heatsink is designed to heatsink the transistor through the junction of the pad area that the transistor is attached to. The paste pattern we chose was small dots ar
Electronics Forum | Fri Jul 19 22:26:32 EDT 2019 | dhanish
Thanks Dave..What is the voids spec for QFN?This is another challenge with the QFN's
Electronics Forum | Tue Mar 08 02:28:03 EST 2011 | nagesh
I have an issue with PLCC Insufficient Heel solder joint fillet.The aperture dimension is : 30 x 100 mils on PCB & on stencil also(1:1 per gerber).Rohs Process. My stencil thickness is 5mils due to presence of Tssop & QFP package & i cannot increase
Electronics Forum | Wed Jul 09 09:27:02 EDT 2003 | MA/NY DDave
Hi Saw a Cross Section picture and thought of you You noted above that you couldn't find any pictures or descriptions of your problem in a few well known sources. It probably is not what you are experiencing yet a soldering defect called land lift
