Electronics Forum: flat lug leads (Page 1 of 20)

pb free component leads

Electronics Forum | Wed Feb 16 17:28:14 EST 2005 | davef

Greg: As we understand it, in your situation: * One 0805 lead solders to board properly * Another 0805 lead does not solder On the 0805 lead does not solder, there does the solder go? * On the pad * On the component lead A common solderability test

Connector with unique leads

Electronics Forum | Sun Feb 28 13:51:56 EST 2021 | bengill

We have a unique connector with flat leads, i.e. the leads leave the connector body flat parallel to the pads. The leads are without a heel, they are flush with the connector body. Moreover, one can't solder beneath the connector because the leads ar

Re: Trimming leads

Electronics Forum | Sat Feb 05 14:51:08 EST 2000 | Bill Petlock

Casimir, The Q and other lead trimmers work extremely well if properly used. Blade life is directly proportional to to the height of the cut. There are a few factors that are very important in trimming. You are working with a solid carbide blade whi

Solder bridging on IC leads

Electronics Forum | Mon Aug 23 03:12:57 EDT 2010 | grahamcooper22

Possible route causes of bridging on fine pitch ICs are; too much paste (stencil aperture wrong), poor print quality (paste smudges during printing), pcb pads not flat depending on the solderable coating, paste has poor cold slump properties, too muc

Re: Detecting lifted leads on QFPs

Electronics Forum | Fri May 28 16:30:39 EDT 1999 | JohnW

| Yes l know this problem keeps cropping up on the forum but l've missed some of the follow-ups. | | Our problem is that the lifting only occurs on 3% of production so actually detecting an improvement is difficult. We're actually having to inspect

Tinned leads and where the component body is defined

Electronics Forum | Thu Sep 03 22:03:32 EDT 2020 | SMTA-64386139

Both conditions are acceptable for this bottom brazed flat pack package. The solder coverage must be within 0.070 inch of the lead/package interface per MIL-PRF-38535, paragraph A3.5.6.3.4.a. While that requirement could allow for a gold gap near t

Tinned leads and where the component body is defined

Electronics Forum | Wed Sep 02 15:02:36 EDT 2020 | SMTA-64387501

We have recently received some pre-tinned "flat lead packages" and the question I have relates to the definition of solder touching the component body of the part. Typically when I have gold lead parts tinned there is a gold gap between the tinned po

SMT solder Covering component surface

Electronics Forum | Mon Jul 01 13:38:01 EDT 2013 | emeto

I am also not sure if the Electrolytic capacitor has a "flat lug leads". I think it is more like a coined lead. I hope other experts can advice.

FLAT LUG LEADS (USBS & SOD123 DIODES) - TOE WETTING

Electronics Forum | Mon Jul 31 03:50:26 EDT 2023 | calebcsmt

Is below the correct interpretation of IPC 610/JSTD requirements for FLAT LUG LEADS (seen on USBs and Diodes mainly) For class 1 or 2, no toe wetting would be required as minimum side joint is only 'evident wetting' and no actual length or fillet he

SMT electrolytic capacitor lead classification is???

Electronics Forum | Fri Nov 14 07:56:49 EST 2008 | davef

Section 9 of J-STD-001 gives you what you need. Further: * Flattened [coined] lead: http://workmanship.nasa.gov/lib/insp/2%20books/links/sections/files/711.pdf * Flat lug lead: Look for the Package Designator �LT� on page 7 of http://www.allegromicr

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