Electronics Forum: flux residuce on test point (Page 1 of 1)

Testing effect of non-clean flux residue on solder joints

Electronics Forum | Fri Nov 03 11:30:29 EDT 2017 | davef

regarding dwl comment, "For low volume hand assembly, deionized water or IPA should work fine." Deionized water: Deionized water is corrosive. It needs to be removed. Proof? Drop a copper coin into a covered jar of DI water and watch what happens ov

Flux residue effects on circuit performance?

Electronics Forum | Sun Apr 28 07:34:34 EDT 2002 | hany_khoga

Dear Tom : I hope I �m not too late. We produce PC motherboards with some buses exceeding the speed of 100MHz . we use no clean flux and it is OK even with the residues you can see under a microscope. But according to our own experience through a mo

Re: White layer appearance on PCB

Electronics Forum | Sun Jan 31 03:28:24 EST 1999 | Jeff Sanchez

| Hello Netters, | | I need some info, Earl or Dave, I have a PCB that exhibits a white layer on solder side. It does not appear to be surface residues (IPA has no effect), but looks like its under solder mask. My first guess is that the LPI solde

Re: White layer appearance on PCB

Electronics Forum | Sun Jan 31 22:55:33 EST 1999 | Dennis O'Donnell

| | Hello Netters, | | | | I need some info, Earl or Dave, I have a PCB that exhibits a white layer on solder side. It does not appear to be surface residues (IPA has no effect), but looks like its under solder mask. My first guess is that the LPI

Re: White layer appearance on PCB

Electronics Forum | Wed Feb 03 04:44:43 EST 1999 | Jeff Sanchez

| | | Hello Netters, | | | | | | I need some info, Earl or Dave, I have a PCB that exhibits a white layer on solder side. It does not appear to be surface residues (IPA has no effect), but looks like its under solder mask. My first guess is that t

Re: More informations on water clean for CSP/BGA package

Electronics Forum | Wed Oct 06 03:58:25 EDT 1999 | Brian

| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n

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