Electronics Forum | Fri Aug 11 09:55:08 EDT 2023 | boyabandaoti
In recent years, SMT patching has become more and more difficult to do. Why? 1. The industry homogeneity competition is more and more enrolled with the SMT patch processing industry. There are not only SMT patch processing in Shenzhen. Everyone in s
Electronics Forum | Mon Sep 13 04:11:27 EDT 1999 | Earl Moon
| | hello | | | | having a problem with one customers bare boards not matching my stencil apertures. i design stencils based on gerber data and reduce up to 15% on some pads. do some board houses reduce pads after receiving gerber data???why would
Electronics Forum | Thu Mar 28 13:19:14 EDT 2019 | davef
There is no industry standard for BTC stand-off height. "IPC-7093A Design and Assembly Process Implementation for Bottom Termination SMT (BTC) Components" just finished "Final Draft for Industry Review" in December 2018. It mentions stand-off height
Electronics Forum | Wed May 29 18:15:18 EDT 2019 | assuredtech
Hello SMTnet, I've been using this forum for several years and have grown to respect what it provides to our industry and enjoy our collaboration of; process knowledge, equipment knowledge and providing resources to share as we continue to grow this
Electronics Forum | Sat May 27 17:21:43 EDT 2006 | smt_guru
Efren, Allow me to make some recommendations. This is my firm's bread and butter, so to speak. Helping startups like yourself achieve their budget objectives, but in the process being innovative and thinking outside of the box. Here are my sugges
Electronics Forum | Tue Jun 20 14:58:22 EDT 2006 | smt_guru
Allow me to make some recommendations. This is my firm's bread and butter, so to speak. Helping startups like yourself achieve their budget objectives, but in the process being innovative and thinking outside of the box. Here are my suggestions----
Electronics Forum | Fri Apr 20 15:49:26 EDT 2007 | Theresa Spear
Instead of using adhesives to glue the back side SMD components and wave soldering them together with the through hole components, our manufacturing engineers choose to process the back side components through reflow oven without adhesives and proces
Electronics Forum | Thu May 10 13:58:26 EDT 2001 | tomgervascio
It sounds like 3D imaging is much better at fault detection for partially visible leads like SOJ packages. Can any of the 2D systems actually do a solderjoint inspection on the outer rows of BGAs or is the angle too acute to accurately look at these.
Electronics Forum | Fri Nov 27 02:09:50 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
Electronics Forum | Fri Nov 27 02:11:17 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
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