Electronics Forum | Tue Jun 06 11:57:12 EDT 2006 | Chunks
IPC 610 says acceptable Class 1 (Class 2, 3 indicator) if they are entrapped/encpsulated balls within 0.13mm of lands or pads. or exceed 0.13mm in diameter. Defect Class 1,2,3: Solder ball violates min electrical clearance. Solder balls not entrap
Electronics Forum | Mon Jul 16 15:49:33 EDT 2001 | Steve
The solder balls you are talking about are caused by too much paste. Reduce the size of the stencil aperatures. Concerning removing the solder balls, the first thing you need to ask yourself is, do I need to remove them. IPC-610, 12.4.10 states, "Ac
Electronics Forum | Thu Nov 29 17:30:07 EST 2001 | davef
You give no clue of what you want to write about. Let's try this: J-STD-001, 8.3.1 Particulate Matter says words to the effect of solder balls / splats shall be neither: * Loose or able to be dislodged during normal service � NOR * Violate minimu
Electronics Forum | Tue Dec 17 12:53:28 EST 2002 | russ
You looked one page to far in the IPC book! Fillet height of 75% is acceptable for all 3 classes. Per IPC 610 rev. C Section 6 table 6.2. A. Circumferential wetting on Primary side (top)between lead and barrel (not anualar ring) Class 1 Not spe
Electronics Forum | Thu Oct 26 11:49:54 EDT 2006 | sms_don
CW, The good news is that you are not trying to use SAC paste with SnPb balls for that would be a void generator due to the ball being liquidous while the SAC paste is still in a flux cleaning stage. Two points to consider: One, voids are not an i
Electronics Forum | Tue Aug 02 22:49:55 EDT 2005 | davef
IPC-A-610D Section 5, shows a variety of photographs of: * Good lead-free solder connections * Lead-free soldering anomalies Hot Tear / Shrink Hole is one such anomaly. This shrinkage effect appears primarily on wave-soldered joints, but can also
Electronics Forum | Mon Jul 16 10:44:29 EDT 2007 | Jacky
Hi All, Recently, we encountered strange defect at our SMT line. We can see solder ball spatter around at one of the component pad. This lead to insufficient solder defect at 1 side of the component. The other side of the component look good(Meet
Electronics Forum | Tue Jul 02 02:50:55 EDT 2002 | ianchan
Hi mates, was going thru the IPC-A-610C Standards, and noted BGA voids stands somewhere between 10%-25% voids permissible in the solder "ball" bump, after reflow process. Was wondering, hypothetical case study, is there any specification for voids
Electronics Forum | Tue Jul 25 13:40:04 EDT 2017 | davegoad
I have some CERSOT-23 transistor packages with castellated terminals. The 4th lead (drain castellation) is electrically connected to the top of the device by the castellation. The castellation goes up the ceramic body and contacts the metal package
Electronics Forum | Tue Nov 28 09:37:39 EST 2006 | GS
Have you seen IPC-A-610 D ? regards GS
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