277 ipc and 2221 results

Electronics Forum: ipc and 2221 (Page 13 of 28)

Re: IPC Standards and ISO 9000

Electronics Forum | Fri Dec 08 14:37:57 EST 2000 | Michael Parker

Roger- No greater confidence builder in the world than to go ahead and jump in with both feet. Just do it!!!

IPC Standard for Acceptable and Reject Criteria

Electronics Forum | Wed Nov 03 09:59:47 EST 2004 | Simon UK

Hi Dennis, I would say that you must meet one of the acceptable critera if you have others list, but it depends. Do you have a specific query in relation to a solder joint or other defect?? Simon UK

IPC Standard for Acceptable and Reject Criteria

Electronics Forum | Wed Nov 03 13:31:28 EST 2004 | russ

Could you give a specific example (sect. paragraph etc) that is giving you trouble? Russ

Your opinion about RoHS and WEEE ?

Electronics Forum | Wed Dec 15 12:47:59 EST 2004 | DasonC

Recommend to check http://leadfree.ipc.org I agreed the lead free is a must for environmental and human health. Not sure how soon they can found out another harmful material

Info/Papers correlating lead protrusion and reliability

Electronics Forum | Wed Mar 16 18:39:55 EST 2005 | KT

I am looking for the same. IPC 610D does mention about the solder fill based on the class (A,B,C). But, there is no exhaustive study that I have come across. Please let me know if you find any. KT

Acceptable per J-STD-001 and IPC-A-610 Class 3?

Electronics Forum | Thu May 23 18:10:54 EDT 2013 | davef

I agree with Rob. These solder connections are unacceptable. BR, davef

Acceptable per J-STD-001 and IPC-A-610 Class 3?

Electronics Forum | Thu May 23 18:40:48 EDT 2013 | rway

I also agree. Even if it did meet specs, I wouldn't let a joint like this out. Reese

OSP and getting full pad wetting??

Electronics Forum | Fri Apr 18 18:06:47 EDT 2014 | davef

Methods that can reduce the wettability of OSP: * Previous heat cycles * Previous cleaning cycles * IPC-1601 "Printed Board Handling and Storage Guidelines" says do not bake prior to soldering * Using improper handling methods BR ... davef

Aperture Adjustments and Etch Compensation on Arrays

Electronics Forum | Mon Sep 23 01:28:13 EDT 2019 | sssamw

Cannot understood your problem very clearly, please check IPC standard on QFN and its mfg process, also check the QFN supplier's recommendation, so can minimize the bridge.

CCGA - Stencil design and Reflow Profiling

Electronics Forum | Wed Jul 24 17:25:01 EDT 2019 | davef

Your solder stencil design should follow all basic rules for solder stencil design are followed in accordance with IPC-7525 including adherence to an area ratio of 2:3 or greater and an aspect ratio of 1.5 or greater.