Electronics Forum | Thu Jan 30 01:38:22 EST 2014 | m_imtiaz
thank for good input, any documented standard available from any well known body (IPC standard)
Electronics Forum | Fri Mar 25 14:33:26 EDT 2011 | davef
IPC-7525 Stencil Design Guidelines
Electronics Forum | Wed Mar 23 05:17:23 EDT 2011 | arwankhoiruddin
Hi All. I want to know what is the IPC/JEDEC standard for solder paste printing defects. From the brochures of SPI Machines, the recognized defects are excessive, insufficient, misalignment, no solder, bridging, and solder shape error. What document
Electronics Forum | Fri Mar 25 06:03:40 EDT 2011 | arwankhoiruddin
Thank you for the reply, Davef. I am thinking if I can get the standard rather than "trial and error". If there is no such standard, is there any experience of what is the range for good and acceptable solder paste (e.g. minimum and maximum percenta
Electronics Forum | Wed Mar 23 11:08:36 EDT 2011 | davef
There is no such standard, nor should there be. The important thing is to make good solder connections. That's IPC standardization focus, defining good results of manufacturing process. The approach that you take in developing the process of making g
Electronics Forum | Tue Jan 07 23:38:08 EST 2014 | m_imtiaz
want to know the tolerance the paste height in the solder paste printing. for example if stencil thickness is 7 mil, what will the acceptance level of paste height ( upper and lower) kindly share if any guidelines or formula for the same
Electronics Forum | Wed Jan 08 08:20:52 EST 2014 | emeto
To most of our boards I give 20-30% tolerance in both directions. From experience if you have big aperture on your stencil, the squeegee will scoop certain amount of paste from this aperture and you will see lower height. Depending on your board supp
Electronics Forum | Fri Jan 24 08:14:24 EST 2014 | davem
m_imtiaz, Over the last 15 years or so I've found that using the stencil foil thickness +2mils/-0mils has worked very well. For example, if you have a 5mil stencil thickness your upper control limit would be 7mils and your lower control limit would
Electronics Forum | Sat Nov 18 21:20:58 EST 2006 | Fer
Dave, May I ask where did you find the 1.5%, or the goal of .005" (or .007") per inch? The IPC-A-600 bow and twist standard calls for a .75% based on the calculation of the test method TM-650, method 2.4.22, which calculates the percentage based on
Electronics Forum | Mon Nov 20 19:49:03 EST 2006 | davef
Sorry for stating this incorrectly. It should been: Bow & twist for bare boards and panels: IPC-A-610 Acceptability of Electronic Assemblies, 10.6: 1.5% for PTH only and 0.75% for SMT, acording to test method TM-650, method 2.4.22 IPC-6012, par. 3.
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