Electronics Forum | Thu May 31 10:21:16 EDT 2001 | davef
On "Flip Chip/uBGA Under-fill Visual Standards" � The third "Satisfactory" [The under-fill if by design should be visible � ], here the notation "if by design" is unclear. Does "according to product documentation" get to the point? The first "Acc
Electronics Forum | Thu Mar 10 15:10:07 EST 2005 | bandjwet
In reviewing the myriad of BGA reliability tech papers there seems to be little commonality in the type of test protocols. There are tests that are industry specific, device vendor specific and customer specific. What guidance in terms of minimum me
Electronics Forum | Thu Aug 05 10:55:09 EDT 1999 | Wolfgang Busko
| | | | | | Hello, | If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem with chip components but
Electronics Forum | Tue Jan 13 12:02:38 EST 2004 | blnorman
We're changing solder bar and wire suppliers and are running impurity tests. Is there an IPC standard that lists acceptable limits for ultra pure, pure, solders for metallic and non-metallic impurities? What is the preferred method to test? We've
Electronics Forum | Thu Mar 30 21:46:56 EST 2000 | Dave F
Reg: This is copy / paste from draft version of IPC 7095 ( issued May 1999 ) ... 7.3 Assembly accept/reject criteria 7.3.1 Voids in solder joint a. Sources of Voids There can be voids in solder balls, or at the solder joints to the BGA, or at the so
Electronics Forum | Thu Aug 09 09:05:09 EDT 2007 | davef
There are no requirements acceptance criteria for baking of board assemblies. What are your customer requirements? The common reasons people choose to bake PCB are to prevent: * Delamination of multilayer boards * Measles, particularly on double si
Electronics Forum | Wed Feb 02 21:56:11 EST 2005 | davef
Based on X-ray imaging, IPC-7095 standard specifies three categories for void size for BGA solder joints. These categories are based on the percentage of joint cross sectional area occupied by the voided area. Class III Small: Void area is LT 9% Cla
Electronics Forum | Fri Oct 09 23:17:05 EDT 1998 | kallol Chakraborty
| | I need to set a cleanliness limit for our incoming boards. I know that some people use 14-10 microgr. sq. in. But how can I determine what is best for me. | | Can anybody tell me if there's a standard for this. | | Right now we are using an Alph
Electronics Forum | Mon May 28 07:30:52 EDT 2001 | bobwillis
Here is a draft visual inspection guide for underfill, please pass this on to the relevant people for any comments or suggestions. I am currently working on the pictures to go with the reference guide. Flip Chip/uBGA Underfill Visual Standards The
Electronics Forum | Sat Aug 07 11:47:47 EDT 1999 | JohnW
| | | | | | | | | | | | Hello, | | | If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem with chi
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