Electronics Forum | Wed Jul 18 11:49:59 EDT 2007 | davef
The auditor may be using "verify" in an ESD Program context. See ANSI/ESD S20.20 [1999], 6.1.3, Compliance Verification Plan. It gives one definition of what the auditor may be seeking. For more on verification programs, look here: http://www.protek
Electronics Forum | Thu Aug 09 19:13:37 EDT 2007 | htran
DaveF, Our customer requirement is to comply with IPC-STD-001 but the J std doesn't specify the bake out temperature for populated boards and the moisture absortion rate. Right now we are baking the populated PWAs after aqueous wash at 80C at 18-48
Electronics Forum | Tue Aug 14 19:49:21 EDT 2007 | htran
My apology for not mentioned the J-STD-001DS. I didn't mean to trick you. Anyway thanks for your inputs. You are the man with the smt knowledge, I am sure that I will be asking you for some more answers again. Thank you for the link. I will loo
Electronics Forum | Mon Jul 14 07:49:50 EDT 2008 | edmaya33
Do we really need to follow the IPC J-STD-001 Solder purity? If so, how to effectively balance the chemistry of Sn63/Pb37 other than adding a pure tin on the solder bath? Is this really needed to monitor in monthly basis?How many kgs of pure tin pe
Electronics Forum | Fri Nov 14 07:56:49 EST 2008 | davef
Section 9 of J-STD-001 gives you what you need. Further: * Flattened [coined] lead: http://workmanship.nasa.gov/lib/insp/2%20books/links/sections/files/711.pdf * Flat lug lead: Look for the Package Designator �LT� on page 7 of http://www.allegromicr
Electronics Forum | Sun May 02 11:44:03 EDT 2010 | davef
J-STD-001 is your base requirement, but MIL and SPACE have stringent requirements for soldering gold plated terminals, e.g. this typical one: http://xweb.nrl.navy.mil/glast/CALDesign/CDE/CAL%20DPD%20Wire%20Cable%20Soldering%20and%20Staking%20Spec%20
Electronics Forum | Thu Sep 05 22:36:38 EDT 2013 | davef
Yes, providing your: * Inbound material does not compromise your process. * Soldering processes apply the proper amount of flux and activate it properly * Material handling does not contaminate your boards Recognize that the IPC requirements of less
Electronics Forum | Thu Nov 29 22:51:18 EST 2018 | jandon
IPC J-STD-001F: 6.2.1 Solder Application: Solder shall (N1D1D3) only be applied to the one side of a PTH except for intrusive soldering. Heat may be simultaneously applied to the both sides of the PTH.
Electronics Forum | Wed Mar 27 04:32:49 EDT 2019 | pavel_murtishev
Charliem, Thank you for the input. Following this logic, in case if there are no soldering issues, pad coverage and voiding levels are within acceptable limits and a gap between BTC and pad let us say 200um, this could be accepted, right? IPC-A-61
Electronics Forum | Thu Sep 27 19:52:28 EDT 2001 | davef
All of the discussion of "environmental controls" are a matter of degree, dependent on the requirements of the product that you manufacture. For example: shops assembling under-the-hood products have different requirements than shops making garage d
