Electronics Forum | Tue Oct 03 17:08:31 EDT 2023 | assuredtech
What Is FR4 Substrate Material? FR4, also written as FR-4, is both a name and a standard rating. The name is applied to the fiberglass-reinforced epoxy-laminated sheets used in printed circuit board manufacturing. However, the name also functions as
Electronics Forum | Wed May 07 21:20:53 EDT 2008 | davef
Causes of Delamination ["Quality Assessment of Printed Circuit Boards" Lund, Preben; Bishop Graphics 1985 0137450354] The reason for delamination is epoxy starvation in the glass cloth layers or an incomplete curing of the base material. It has been
Electronics Forum | Wed Mar 14 17:52:49 EST 2001 | davef
6 Work Life Test 6.1 Obtain a stencil with 15 to 20 rows of a series of 0.025 by 0.050 inch apertures spaced 0.050, 0.040, 0.025, 0.015, 0.010, 0.010, 0.025, 0.040, 0.050 inches apart. See Appendix 1. Source of supply: Metal Etching Technology.
Electronics Forum | Thu Oct 26 13:56:08 EDT 2000 | ptvianc
Hello: Pre-baking laminates should only be performed:(1) to meet contractual agreements or (2) in response to an actual defect that can be traced to PWB water absortion. Besides the fact that a pre-bake is an enormous process "bottleneck," it also
Electronics Forum | Wed Oct 29 06:17:45 EDT 2014 | julianf
As stated in the title I would like to know the thermo-elastic material properties, most preferably the E-modulus and CTE in x- and y-direction, for Epoxy/E-glass laminates and/or prepregs for various fibreglass cloth styles. Datasheets only give ro
Electronics Forum | Thu Oct 26 09:10:30 EDT 2000 | ptvianc
I am not familiar with the "HALT" terminology. Do you mean HAST testing? As for thermal fatigue, the most severe conditions are typically those cited for military and/or satellite applications. There are several temperature ranges that are used to
Electronics Forum | Thu Apr 22 16:15:26 EDT 1999 | Steve Gregory
| Could anyone recommend a good depanization tool for a PCMCIA | panel which has breakaways. For several reasons, we decided to | go with this approach rather than scoring and I'm less than | pleased with the punch presses we currently use. Any h
Electronics Forum | Wed Oct 07 15:25:02 EDT 1998 | Joe P.
Hi Everybody | | Is anyone aware of the possible causes that may lead to voids in the solder bumps after assembly. We assembled some dice on thin substrates and after assembly, void formation in the solder bumps were observed. | We have alread
Electronics Forum | Wed Jul 09 04:57:11 EDT 2003 | Matt Kehoe
Our company applies solid solder to surface mount lands. While processing a micro BGA design we had some pads fall off, peel, whatever you might call it, from the surface of the board when touched "GENTLY" with the tip of a blade to remove a small s
Electronics Forum | Mon Apr 12 22:22:01 EDT 2004 | davef
Large voids are common in via in pad [seach the fine SMTnet Archives for earlier laments], especially in blind via. Observations on your via out gassing theory: * If the copper plating on your via is GT 1 thou, there will be no outgassing from the
