Electronics Forum | Thu Jul 06 16:13:28 EDT 2017 | barryg
Hello everyone, I was curious if anyone knows what criteria there is for layer to layer registration. I have looked at ipc-600 and 601 and have not found anything or am missing something. We had a small qty. of pcbs sent to a customer and some inner
Electronics Forum | Thu Jul 06 21:24:10 EDT 2017 | heros_electronics
Hi Jack, Haven't you done 100% E-test? there is a registration tolerance. CCD+/-2mil, Manual+/-4mils according to our manufacturing capacitites.
Electronics Forum | Fri Jul 07 09:39:19 EDT 2017 | barryg
Our PCB supplier was supposed to be doing 100% ET but a few of his PCBs were not, and were not marked as tested, so now we are supersensitive. We received some PCBs from a new supplier and one of our inspectors noticed some shift. I was looking for s
Electronics Forum | Thu Aug 31 09:12:54 EDT 2017 | hxamalia
Hello ALL Good day , it is Amalia from HX Circuit Technology Co.,Ltd in China, we are a prefessional PCB factory with many years. We are focusing on quick lead time for PCB with good service . please contact with me now ,thanks Email: amalia@hx-c
Electronics Forum | Fri Nov 30 12:31:06 EST 2012 | zero260n4
checking the solder paste layer what is suggested in order to perform a robust DFM
Electronics Forum | Fri Sep 28 07:42:07 EDT 2007 | zanolli
We have the need to verify that proper intermetallic layer between a 100% Sn plated contact and the solder joint is being formed. Never having done this before: Is there any specifications, etc. that we can use as acceptability criteria?
Electronics Forum | Thu Nov 29 11:27:59 EST 2012 | zero260n4
I was asked a question; if you are doing a DFM on a solder paste layer what do you look for? it stumped me
Electronics Forum | Thu Nov 29 14:11:33 EST 2012 | davef
When you say "solder paste layer," what are you talking about: * Post-print / pre-placement quality inspection * Post-reflow solder inspection * er what?
Electronics Forum | Sat Dec 08 00:09:24 EST 2012 | jlawson
Mentor(Valor) has dfm softwares that not only looks at the stecnicl layers buy can look at other impacts that could effect the optimisation of the stencil design, ie solder mask layer tolerances defined from fabricator-design etc - this is a upper en
Electronics Forum | Fri Nov 30 08:37:51 EST 2012 | ericrr
What is DFM? Design for Manufacturability?
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