Electronics Forum | Wed Jun 10 18:50:36 EDT 1998 | Earl Moon
| | | Does anyone have any info./studies on what the percentage or PPM defect rates are for each part of the typical SMT process. | | | Example: | | | Screen Print = 45% of total defects | | | Component Placement = 25% of total de
Electronics Forum | Tue Nov 28 22:35:30 EST 2000 | rabell
We are currently in release 1.4 and 1.5 of the majority of our courses, partly because we do fix minor errors that do crop up, and release maintenance updates. I infer from your comment that you take exception to one or more of the test questions in
Electronics Forum | Fri May 28 16:30:39 EDT 1999 | JohnW
| Yes l know this problem keeps cropping up on the forum but l've missed some of the follow-ups. | | Our problem is that the lifting only occurs on 3% of production so actually detecting an improvement is difficult. We're actually having to inspect
Electronics Forum | Mon Sep 09 12:00:01 EDT 2013 | proteus
I have a 208 pin QFP that due to manufacture obsolescence I have to get them form the broker market. I've had several issues with the parts including; bent leads, leads that don't take solder very well, co-planarity problems, and DOA fallout after a
Electronics Forum | Tue Oct 26 18:16:01 EDT 1999 | Dave F
Jerry, I know I'm off target, but I don't care. Three things: 1 We don't see the level of malformed leads that would pay-back a $30k investment in 10 years. (Of course, we haven't talked about volume, but you can't have very much volume, can you??
Electronics Forum | Tue Jul 14 07:37:31 EDT 2009 | tony_d
Hello Reese, We currently own two MIRTEC MV-3 desktop machines and one MV-7 inline machine (so you can tell right away that I am a little biased.) We had an opportunity to evaluate both the YESTech and MIRTEC machines on our production floor. The
Electronics Forum | Mon Oct 02 16:31:17 EDT 2000 | Larry
I have seen people take old stencils and cut out land patterns, place the component over the land pattern and use a orange stick to move the leads back into place.
Electronics Forum | Fri Apr 16 09:40:04 EDT 1999 | Gerry G
While trying to sell me a low temperature baking system for SMDs the salesman mentioned that the 125C for 24hr bake had been known to cause co-planarity defects. I thought I'd ask some experts. Any help guys?
Electronics Forum | Wed Oct 01 15:06:50 EDT 2003 | davef
You're thinking correctly. Concentrate your recipe development efforts by profiling directly on the pads [that some fine designer forgot to thermally isolate properly] of those pesky corner leads that don't solder well.
Electronics Forum | Tue Sep 14 06:08:46 EDT 2004 | sc
The general control on QFP fine-pitch coplanarity is +3mils. suggest to look at the re-use of thrown out component from SMT machine. If the component pack in std pack, then most probably the lifted is due to processing, not incoming as the packaging
