Electronics Forum | Fri Jan 15 09:27:18 EST 1999 | Earl Moon
| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat
Electronics Forum | Sat Mar 24 03:06:55 EDT 2007 | aj
Hi Mika, We came across some difficulties with this type of device a couple of years back . After the proto run we needed to touch up the outside fillets to get stability and product to pass test. ( even though the manf. stated that there is no fill
Electronics Forum | Mon Aug 28 12:41:35 EDT 2000 | JAX
MoonMan, I'll take a crack at the list. Feel free to answer the ones I don't! 1. Solderability is a parameter which indicates how well a component can be soldered. As far as Solder Termination Coatings go, here are some up�s and down�s of a few. Ha
Electronics Forum | Thu Jun 08 01:46:00 EDT 2023 | camilleyang3
To prevent BGA (Ball Grid Array) issues related to SMT (Surface Mount Technology) solder resist when fabricating a PCBA (Printed Circuit Board Assembly), you can follow these guidelines: Design considerations: Ensure proper spacing between BGA pads
Electronics Forum | Thu Apr 04 05:33:19 EST 2002 | ianchan
Hi, hope this helps : 1) BCC (bump chip carrier) production for us, was with a 5mils Stencil. The outer perimeter smallish pads are not much of a problems. For the central large pad, we split the paste print (corresponds to the Stencil apperture op
Electronics Forum | Wed Oct 27 16:55:38 EDT 1999 | Joe Herz
Jerry, In our house we generally run a glue bottom last but people do it both ways. Our logic revolves around protecting components from being knocked off the board during handling and processing prior to wave solder (this is most important with sm
Electronics Forum | Fri Oct 01 10:04:20 EDT 1999 | Andrew William Dalrymple
I am currently in the middle of a company wide war and I'm looking for data (AMMO). Here are the problems: 1) I am looking for anyone who has done or seen any reports on Thermal Shock to smt parts and/or via holes caused by Soldering Irons at rewor
Electronics Forum | Thu Sep 30 13:37:08 EDT 1999 | Dave F
| | I am having problems processing immersion gold boards. The achieved solder joints appear acceptable a la IPC-A-610, but the resultant joint does not fully cover the land, i.e. you can still see an outline of gold pad. | | What is the best way to
Electronics Forum | Mon Aug 22 10:33:23 EDT 2005 | davef
Q1. What is recommended viscosity standard? A1: There is no standard. ASTM D4040-05 "Standard Test Method for Rheological Properties of Paste Printing and Vehicles by the Falling-Rod Viscometer" is a test method that might work. For more, look her
Electronics Forum | Wed Jun 21 11:09:37 EDT 2006 | samir
Muse, I agree. There has been much debate but the previous scenarios discussed in the forum have been regarding the SAC/RoHS BGA and Sn-Pb paste. I have successfully collapsed a SAC BGA with a Sn-Pb paste using the "hybrid" profile that Amol refers
