Electronics Forum | Fri Jan 03 10:26:15 EST 2020 | emeto
Some of the voids are questioned and they might easily be over 25%.
Electronics Forum | Fri Jan 03 13:36:01 EST 2020 | emeto
We use low voiding formula from Indium.
Electronics Forum | Tue Jan 07 17:33:26 EST 2020 | SMTA-Norah
Were the boards baked out before soldering? Is there plated over vias in the pads?
Electronics Forum | Wed Jan 08 10:04:29 EST 2020 | emeto
We don't have plated vias on these pads.
Electronics Forum | Fri Jan 10 14:37:02 EST 2020 | emeto
Zack, would you recommend longer TAL or higher peak temp or both together?
Electronics Forum | Tue Jan 14 13:28:44 EST 2020 | cyber_wolf
Your profile looks textbook.
Electronics Forum | Fri Jan 17 02:49:11 EST 2020 | jakapratama
Yeah, that's a nearly uniformed ramp up profile, I can't see anything's wrong with that.
Electronics Forum | Tue Dec 31 11:48:36 EST 2019 | emeto
Hello experts, I have a 50mmx50mm LGA on a PCBA. I Would like to decrease voiding in these joints and I wanted to hear about your techniques to decrease voiding. Stencil is currently 5mil. SAC305. ENIG finish.
Electronics Forum | Fri Jan 03 02:03:58 EST 2020 | sssamw
What's your target for voiding? I cannot see it violate 25% of solder joint area. Process setting and PCB design can impact the voiding, many factors, such as PCB pad, stencil aperture and thickness, re-flow profile, solder paste, etc.
