Electronics Forum: mask blanks (Page 1 of 1)

Wicking-solder found under mask

Electronics Forum | Fri Jul 06 18:19:41 EDT 2001 | davef

The senior staff have the pictures!!! Oh, that�s just GREAT!!! What the blank are these gerbils doing with �em? Nothin�!!! They�re probably sitting in a folder on whatzisname�s desk, until he has "a change to study them more". [Like he�s going t

Re: solder mask

Electronics Forum | Sun Aug 15 05:45:15 EDT 1999 | Brian

Boca, Dave Sorry, but I cannot let this go. I'll go along with you that, at the time that the Montreal Protocol was initially signed (September 1987), there was no scientific proof that CFCs etc. were causing ozone depletion. There was, however, ve

Solder balls after wavesolder

Electronics Forum | Wed Nov 14 20:28:24 EST 2001 | davef

Not to worry. Just run the boards through the cleaner. It will remove all the solder balls. The gross filter on your washer will collect all the solder balls. Coo eh? ;-) How to cure SM? Is your mask UV, er thermal? After learning the type, you

Goldfinger protection

Electronics Forum | Fri Jan 02 17:47:21 EST 2004 | gpaelmo

Yes, We have done away with masking with kapton 8 yrs ago. As long as the goldfingers are leading edge you can use one of these: 1. rubber goldfinger boot/glove - contact east use to carry them...don't know if they still do. 2. fiberglass glove - ma

Best/Common Practice in Blank PCB QC

Electronics Forum | Tue Feb 25 10:32:09 EST 2003 | davef

I don't know the precise scheme, but it goes something like this ... WHAT TO DO * Use the general work instruction that applies to all boards. It goes into dimension and hole checking processes. It talks to visual instection of solder mask, solder

PBGA vias throwing solder balls

Electronics Forum | Tue Sep 14 14:52:22 EDT 2004 | Carol

During processing, the solder in the vias reflows and forms solder balls. PCBs have solder in random PBGA vias from the board manufacturer.The manufacturer says this is a result of the HASL process and is unavoidable. We use HASL finish, multilayer,

Re: DFM / DFT information

Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F

=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so

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