Electronics Forum | Fri Aug 20 00:11:05 EDT 1999 | Rick Holmes
Anyone out there using OSP with double sided reflow and selective solder pallets? I am having trouble testing through what is left of the Entek Plus on the test pads.
Electronics Forum | Fri Aug 20 05:17:25 EDT 1999 | Earl Moon
| Anyone out there using OSP with double sided reflow and selective solder pallets? I am having trouble testing through what is left of the Entek Plus on the test pads. | Think rotary. Earl Moon
Electronics Forum | Wed Jan 21 16:55:22 EST 2004 | patrickbruneel
Hi, Are you testing bare boards or soldered boards. Are the test probes in contact with soldered pads or contacting the copper with the osp coating (not soldered). If you could clarify this it would be easier to give some hints for probable causes.
Electronics Forum | Wed Jan 21 05:01:10 EST 2004 | sd
Does anyone have any reports on OSP pcb finish and ICT Testing? Having a problem with contact issues.
Electronics Forum | Thu Jan 22 09:21:45 EST 2004 | davef
Oh, another thing, we do not like to probe copper. It's hard, compared to solder, and beats-up the probes too much. [As Patrick Bruneel states in this thread.] Consider reflowing paste on your test pads.
Electronics Forum | Tue Oct 26 08:41:56 EDT 2004 | Bob R.
When we first got into BGAs on ENIG we were getting joint cracking at in-circuit test. The joints were breaking in the Sn-Ni intermetallic. We did a lot of pull testing while working with our board suppliers and our conclusion was that pull testing
Electronics Forum | Fri Nov 15 15:02:37 EST 2002 | MA/NY DDave
OK I know it is funny to have two different PWB/PCB processes, one for pre production and one post production yet it is possible if controlled and implemented in a strategy. In debug if your company's experience has been for a repeated need to do IC
Electronics Forum | Tue Aug 23 13:03:14 EDT 2005 | davef
What's the point of such a test? * If you are operating a board in an environment that keeps the board at a temperature that is close to causing delamination, why not design a board that can tolerate such an operating environment, rather than contin
Electronics Forum | Sun Jul 29 21:33:30 EDT 2001 | CAL
Your Ionograph and Zero-ion Values are set by you. There is no raw pass of fail criteria only the limits you set up. Ionograph is great for bare board resistivity (salt) test just as a pass fail for incoming inspection but this is all per your facto
Electronics Forum | Fri Jan 03 12:12:22 EST 2003 | richard
Good day and thanks for your comments Mike, What did I understood from your notes� 1) ROSE test (�extracting solution�) is probably good enough (with good equipment) to penetrate the space under my micro BGA. 2) I should test 2 parallel batches of
