Electronics Forum | Thu May 14 19:05:02 EDT 1998 | Mike Konrad
Dave, Ionic contamination testers are considered to be a valuable tool to determine the cleanliness of both bare boards and post solder boards. There are some instances when SIR testing is more suitable for determining cleanliness than ionic contamin
Electronics Forum | Tue Jul 11 16:17:22 EDT 2006 | jimc
Need help with an 1994 vintage Alpha Metals Omegameter 700 (OM700) Ionic Contamination tester. These machines apparently came with a unique password to access the configuration. The original factory-configured password has been long lost. I'm wo
Electronics Forum | Tue Jul 27 13:50:52 EDT 1999 | Mike Konrad
Aqueous Technologies manufactures the Zero-Ion ionic contamination tester. The Zero-Ion utilizes dynamic-based technology and has been assigned the highest equivalency value by the NAWC. It is among the most sensitive of all of the military-approved
Electronics Forum | Tue Jun 12 18:06:17 EDT 2001 | davef
The criterion you use will depend on the test method you select. For minimum requirements, look at J-STD-001C, Para 8, "Cleanliness Requirements". I figure that you�d measure the residues on a lot of your current product, measure the res on a lot o
Electronics Forum | Wed Oct 06 00:26:04 EDT 1999 | Karlin
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Wed Oct 06 08:41:42 EDT 1999 | Dave F
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 12:03:12 EDT 1999 | Graham Naisbitt
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 23:36:28 EDT 1999 | karlin
| | | Hi, | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | Question: | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z
Electronics Forum | Fri Oct 08 02:31:07 EDT 1999 | Brian
| | | | Hi, | | | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | | | Question: | | | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowab
Electronics Forum | Mon Jan 08 20:57:52 EST 2001 | Dave F
Are you talking about bare board cleanliness or assembly level cleanliness? Bare board cleanliness is still primarily measured by resistivity of solvent extract (ROSE) using instruments such as Omegameters and Zero Ions. What is considered as "acce
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