Electronics Forum | Fri Sep 24 09:57:54 EDT 1999 | Boca
| | Is there a standard rule/guide for the orientation of pcb's in a panel for panelised board (specially for routed panel). | | i often get this question from peeps here and i kept telling them that it depends on how it affects the process. | | than
Electronics Forum | Thu Feb 06 14:47:50 EST 2003 | MA/NY DDave
Hi "some customers/designers want to have via holes to be present in the PCB pad, due to some belief that it helps in heat dissipation. " As I think about this I don't know exactly why they would be concerned. I can imagine in some exotic products
Electronics Forum | Mon Aug 30 06:47:18 EDT 2010 | arjan
We having issues installing the Linear Tech LTM8023. We have different soldering results in our PBfree testruns. The voiding and solderball rate is not stable (random positions and sizes). The pcb's (gold finish)are prebaked, the LGA's are stored in
Electronics Forum | Thu Sep 21 17:50:43 EDT 2000 | Bill Boles
Does anyone have a quick reminder for a PCB with immersion gold surface finnish going through a reflow profile: Which of the following statements is more correct? A: In order to minimize gold in the intermetallics of the solder joint, the board temp
Electronics Forum | Tue Jul 20 08:32:37 EDT 1999 | Dave F
| Could someone please tell me if it is possible that erroneous 'leakage current' readings in an instrument could be inheritated by the type, design and fabrication of the PCB itself, if so then where could I find information relating to this subject
Electronics Forum | Tue Jan 29 13:06:40 EST 2002 | Sergio Vito - Alan Patrick - Cristiano Dick
Dear sirs, We are experiencing problems with lines of lead formed inside the solder joint. In others words, there is a problem with the formation of the solder joint, after analyses on a microscope we can see the lead grouped in some positions. This
Electronics Forum | Tue Feb 11 13:12:25 EST 2003 | Jim Mills
Use a PCB fab house that is capable of "Conductive Via Filling" is the way to do it right. A conductive epoxy is used to fill the drilled via PRIOR to final plating. After final plating, the surface of the "Filled Via" will appear to be the same as t
Electronics Forum | Tue May 04 22:54:54 EDT 2004 | davef
Yeh, the IPC courtyards are for old ladies. I want to say that at one time IPC was talking about a new set of rules. Maybe, 7351 - SMT Footprint Design Guidelines??? Anyhow, Jim Blankenhorn at SMTPlus [ sales@smtplus.com ] has done THE best job o
Electronics Forum | Mon Jul 17 15:18:31 EDT 2006 | d0min0
Hello there, I'd love to have HR at 50-55%, but also temp at 21-23 deg C, with hot start of summer in Poland, we have on prod.floor close to 30 deg C and 30%HR, it is really difficult to print properly and to get pcb through oven without problems...
Electronics Forum | Fri May 01 07:22:56 EDT 2009 | kareal
In my project of flip chip PGA production , I found serious delamination in interface of solder mask and first layer copper trace of substrate after UHAST 96hrs( 130C, 85%RH) reliability test. The delamination are always around one type solder bump,
Products, services, training & consulting for the assembly, rework & repair of electronic assemblies. BGA process experts. Manufacturers Rep, Distributor & Service Provider for Seamark/Zhuomao and Shuttle Star BGA Rework Stations.
Training Provider / Manufacturer's Representative / Equipment Dealer / Broker / Auctions / Consultant / Service Provider
1750 Mitchell Ave.
Oroville, CA USA
Phone: (888) 406-2830
