Electronics Forum | Thu Oct 25 13:35:47 EDT 2012 | davef
Here's a paper that may help http://www.ipcoutlook.org/pdf/assembly_challenges_bottom_terminated_ipc.pdf Temperature Impact * Profile didn’t have a significant impact on voiding. * Voids slightly increased with higher temperature. Reflow Atmosp
Electronics Forum | Thu Jun 10 06:15:45 EDT 2010 | muarty
We currently have a project requiring us to place multiple QFN devices (of various sizes). The pick an place is not a problem at all, where we are seeing 'problems' is that 3 of the devices are being place on locations where the ground pad have plugg
Electronics Forum | Mon Jun 01 16:48:16 EDT 2009 | stevezeva
Mika, Have you ever worked with a 3-row I/O QFN? QFN180 to be exact? Steve
Electronics Forum | Tue Jun 15 22:31:06 EDT 2010 | Mag10
Depending on the how you plug the via, the void level can significantly affected. If you have via plugged from the bottom side; i.e. opposite side of the component, you will see alot of void due to entrapped air in the via hole. I found work best wh
Electronics Forum | Fri Jun 11 03:14:03 EDT 2010 | muarty
Thanks Dax, We currently employ a stencil aperture design pretty much similar to that you describe. And you are correct in what you say about the thermal demands almost dictating the allowable voiding level. We have suggested to our customer that th
Electronics Forum | Fri May 15 10:04:59 EDT 2009 | aj
Hi all, Is there any standard for percentage voiding on the center thermal pad on a QFN? We use the dot matrix array for paste to allow for outgassing etc, but we have had a couple of xray inspection "fails" for voiding on this pad , in or around 3
Electronics Forum | Thu Jun 10 16:42:11 EDT 2010 | daxman
Hi Muarty, We've had a lot of experience with QFN's now. Several years ago we started testing various design methods of the via arrays as well as paste apertures to cover the arrays. There has been some time that has passed now since these packages
Electronics Forum | Wed Jun 16 07:35:28 EDT 2010 | scottp
Rather than tent the thermal vias, we use a small annular ring of soldermask around them and only print paste in the areas between the vias. Any way you go you're going to have voids under QFNs, so we just try to make it repeatable so our designers
Electronics Forum | Tue May 19 15:06:36 EDT 2009 | c111
we had many problems with this. there is no standard that I could ever find. we came up with our own after weeks of headaches. we use 25% as our guide line we use window pain only for the center paid to allow for out gassing and reduce 15-20% globaly
Electronics Forum | Sat May 30 01:31:49 EDT 2009 | mika
make 4 square rounded corner apertures on the ground pad and the total reduction of 20 % (80 % solder paste). Then you still be able to solder the terminals around. Don't worry to much of the void's. Just following my tips and you will be fine. The
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