Electronics Forum | Wed Feb 15 15:41:46 EST 2006 | russ
Possibly a retention clip that would snap into the board?
Electronics Forum | Wed Jan 02 04:05:46 EST 2002 | ianchan
Well usually QA keeps the COC and x-section samples, for a designated minimum time period of 6 months, this time period is not set in stone and is defined by your ISO records retention period...each company bears varient importance to the retention o
Electronics Forum | Wed Aug 17 08:36:15 EDT 2011 | rway
It's unlikely that this is the root cause. The battery may be dead, but the entire board is dead. This battery is most likely used for data retention for volatile memory as a battery backup.
Electronics Forum | Fri May 19 10:39:19 EDT 2000 | Boca
Ed, I workded with punch and replace fabs yeeeeears ago, major pain! Dave's right, planarity is the biggest problem, then inconsistent retention in the panel, then ANY retention in the panel. If you can get paste on them, you may be able to place
Electronics Forum | Fri May 19 10:41:06 EDT 2000 | Boca
Ed, I workded with punch and replace fabs yeeeeears ago, major pain! Dave's right, planarity is the biggest problem, then inconsistent retention in the panel, then ANY retention in the panel. If you can get paste on them, you may be able to place
Electronics Forum | Tue Apr 14 15:50:45 EDT 1998 | Bob Barr
Justin, Thanks for the response to my dilemma. For once it's not just me! The parts seem perfectly solderable, but I will try the modification to the profile you suggested. I wonder if the retention clips may be letting loose from the holes they a
Electronics Forum | Thu Jan 26 15:16:56 EST 2012 | raranchado
Anybody knows how to use TiMMS Traceability? We're not using the application anymore 'cause we replaced it but server still up for record retention. The engineer who managed this one already left the company and now customer asking for the records. I
Electronics Forum | Wed Jun 08 12:30:38 EDT 2016 | deanm
Lead forming can provide retention during wave soldering. There is the simple offset method, the dimple and compound forms. All of these are outlined in IPC-AJ-820A. It would probably require automated lead forming equipment using special dies. GPD m
Electronics Forum | Fri Dec 27 13:16:18 EST 2019 | slthomas
Can you describe the failure mode of the soldering defect, i.e., is it failing to meet the height requirement for a castellated termination due to not wetting of the component terminations, or not wetting the pads sufficiently, or....? We install a
Electronics Forum | Tue Nov 28 14:07:20 EST 2000 | Ashutosh Agate
Hello Dr. Abell! We are a small co. from India already running class room training programs in ESD as well as SMT. Have recently added web based training programs in SMT. I have read through yr profile & I find you have worked in the area of Distance
