Electronics Forum | Wed Aug 22 02:50:59 EDT 2012 | robertwillis
Are you having any process problems with Package On Package Assembly? If so why not spend a few hours with the POP Team at SMTA International? You have a great opportunity to see, hear and experience POP in October. However if you really can't join
Electronics Forum | Thu Aug 30 21:25:17 EDT 2012 | kahrpr
And that is where I see the problem. When companies have failures that are unexplained they blame ESD. It’s the scapegoat failure. And the industry through fear has us so paranoid We have companies worrying whether if your hair is 2 inches long or 3
Electronics Forum | Fri Aug 31 11:17:51 EDT 2012 | markhoch
My answer is f) ALL OF THE ABOVE. Depending on the type of equipment needed, I first research possible suppliers using the interwebs. I then request more information from any possible suppliers that I may find. Then I'll contact a local rep to see i
Electronics Forum | Mon Sep 17 03:59:52 EDT 2012 | stivais
Hi guys, We have an interesting case we haven't seen before (see the picture below) http://postimage.org/image/lu2f4ae55/ Solder balls form on unpopulated pads after reflow. 1. Reflow profile is fine. 2. Stencil thickness / paste volume is also f
Electronics Forum | Tue Sep 25 11:50:37 EDT 2012 | davef
Ken ... I resized your picture so that it fits on the page better. Continuing with your outgassing through the solder pads theory, how thick is the copper on the pads? I don't expect to see outgassing through pad that are a thou or more in thickness
Electronics Forum | Wed Oct 03 19:28:58 EDT 2012 | rgduval
Given that you're seeing it on nearly every part, we tend to lean towards Dave's explanation. We wouldn't expect outgassing from the pad to be an issue (at least, we've never heard of it before, which doesn't, necessarily, eliminate it as a potentia
Electronics Forum | Thu Oct 25 13:33:18 EDT 2012 | cyber_wolf
Ken, The photo looks like results I have seen because the gold flash was too thick on the board. This causes a condition known as gold imbrittlement. You may want to get an analysis of the plating thickness. I'm not real experienced with immersion si
Electronics Forum | Tue Oct 09 11:17:56 EDT 2012 | 18424
Hello All, I have PCB's in a 30 up panel that have signs of improper solder mask adhesion. Per IPC 6012 they specify a maximum of 5 Percent allowed to have problems adhering to base laminate per class 2. I am trying to figure out if this 5% is for th
Electronics Forum | Mon Nov 19 06:06:28 EST 2012 | ericrr
Hi ENIAC That table is part of a mush bigger article I was putting together, and will post somewhere at this website soon, as a one stop complete information. The hold up was Electrolytics and Tantalums code is different but there is no way to t
Electronics Forum | Mon Nov 26 16:07:56 EST 2012 | jerlong
Greetings, Does anyone know where to find a tape and reel flatness specification? Looking at the EIA 481-B standard, there is no reference to the tape flatness (the images shown may "imply" flatness from one side of the tape to the other, However I
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