Electronics Forum | Mon Sep 21 00:11:14 EDT 2009 | darrenj
We have a TP9 with a centering motor issue. (TPSYS Ver 2.5.3) The error message F-MOT-SETDYN C/3 Upper endpoint outside limits is shown during C-motor initiation. I've looked in the service program and also the parameters in TPSYS but can find no m
Electronics Forum | Mon Nov 25 00:45:35 EST 2013 | igorfo
Thank you for advice, But main concern how to detect the problems with BGA on SMT line, and how I can validate "good" or "bad" profile. PS: SPC said that process Cpk 2, temperature profile in the upper spec limit for TAL and peak temperature.
Electronics Forum | Fri May 26 17:06:21 EDT 2000 | Dave F
Guys: Folk at EOSEAD told me two things on this: 1 Yes "All process essential insulators that have electrostatic fields that exceed 2000 volts should be kept at a minimum distance of 12 inches from ESDS items." is correct. 2 The latest revision to
Electronics Forum | Sat Apr 21 04:39:45 EDT 2012 | brotakul
I am using different equipements for SPI such as Koh Young and Cyber Optics machines. I am looking for implementing a general procedure (SWP) for setting LSL's and USL's on the products on which the customer does not specify any limits on the solder
Electronics Forum | Fri Jan 24 08:14:24 EST 2014 | davem
m_imtiaz, Over the last 15 years or so I've found that using the stencil foil thickness +2mils/-0mils has worked very well. For example, if you have a 5mil stencil thickness your upper control limit would be 7mils and your lower control limit would
Electronics Forum | Tue Apr 13 09:50:18 EDT 1999 | Dave F
| Hello. | | I'm now investigating the current technological issues | on surface mount devices. | For example, I want to know the limitation of | the surface mount machine. | | Where can I get the materials for this purpose? | | Thank you | Cho
Electronics Forum | Fri Dec 21 10:12:46 EST 2007 | ck_the_flip
Operator, Think "opposite". You actually want to MINIMIZE the ramp-up rate. Think about 2 - 3�C per second as your upper limit for ramp up. You don't want to go more than 4�C per second for thermal shock reasons. All of this, of course, depends
Electronics Forum | Thu Sep 17 15:21:50 EDT 2020 | lpbro
For height, I start +-2mil usually. For 3mil stencils, my lower limit starts at 1.5mil, upper is 5. If the area is chem ethed, I normally add .5 to the stencil height. My default volume is 60 - 160%. Then print specs are adjusted till I see fit, then
Electronics Forum | Thu Aug 27 05:49:53 EDT 2015 | alexeis
Hi, To calculate both values you need: 1. Theoretical speed of all machines (Printer, SMT, Reflow). This is a basic upper limit value of speed. Use it for calculate a maximal theoretical values as upper limit. For real values, read next. 2. High r
Electronics Forum | Mon Dec 06 13:32:47 EST 1999 | Bob Smith
CPk is a measure of the process variance with respect to the acceptable upper and lower limits. In your case it would be the accuracy of placement. The exact position of a chip ideally would be dead centre on the pads however in real life that positi
