Electronics Forum | Wed Mar 23 22:29:21 EDT 2011 | nkinar
I have a few prototype circuit boards with BGA footprints where some (but not all) of the vias have been placed too close to the pads. During reflow, some of the solder from the balls flowed into the holes. Only one of the pads under the BGA is not
Electronics Forum | Wed Jun 24 18:50:55 EDT 1998 | John Silvestri
Has anyone seen a problem with solder under chip components, in-between the glue and the component or in-between the mask and the component? We seen both. What could be causing this? This has only been detected on one of our products. All the rest w
Electronics Forum | Wed Aug 09 22:11:46 EDT 2000 | Dave F
Mark: The best routing of test vias for BGAs is to keep them far away from the device. We route test pads for the outer two rows of balls and use vias as test pads for the inner rows of balls. Your bottom-side layout is fine. Yes, on the top-side
Electronics Forum | Wed Jan 30 06:45:01 EST 2002 | yaq
Hi, Has anyone done some research (measurement/simulation) on the effect of PWB vias on solder ball temperature of the component? Would this have some effect on solder joint reliability especially during power cycling? Any comments will be appreciat
Electronics Forum | Thu Jan 31 04:48:04 EST 2002 | yaq
Hi, Has anyone done some research (measurement/simulation) on the effect of PWB vias on solder ball temperature of the component? Would this have some effect on solder joint reliability especially during power cycling? Any comments will be appreciat
Electronics Forum | Thu Aug 21 08:33:09 EDT 2008 | davef
There is no standard as such. It's easy to see why. It's too complicated and has such a small payoff. Standoff is comprised of: * Package height * Solder thickness between the pad and the component lead * Delta of pad thickness and solder mask For p
Electronics Forum | Wed Jan 12 20:20:54 EST 2000 | Bene
I had the opportunity to spend time with a demo and one on one with the inventor of the Ersa scope inhouse a few months ago. I see the scope complimenting X-ray inspection but not as a substitue. It allows you to view attributes of a solder joint t
Electronics Forum | Fri Jul 20 13:50:22 EDT 2018 | vchauhan
This question is regarding stencil design: I am having voids under QFN TI P/N LMZ20502SILT. I have attached component pic. Signal pin is 18X16 mils. Center pads are 31 mil sq. Initially I had stencil done with one mil per side reduction on signal pad
Electronics Forum | Fri Aug 24 13:21:59 EDT 2018 | babe7362000
What do others use as far as solder paste type, stencil thickness and aperature size for a .4mm Ball Pitch CSP. Ball diameter is .3mm. Please let me know your thoughts or what you use. Thanks
Electronics Forum | Wed Apr 27 20:55:10 EDT 2005 | KEN
One thing that may have been over looked: Not all solder pastes are created equal. Period. The best way to avoid these situations is to characterize you material (and your process). The fact is you could try every aperture shape under the sun....a
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