Electronics Forum | Fri Jul 27 09:47:20 EDT 2018 | davef
Adding to Rob's suggestions ... One of the theories about voiding in thermal / ground pads of BTC is: Solder starts melting at the edge of the pad and moves inward towards the center of the solder mass. This traps flux volatilizes. So, there needs t
Electronics Forum | Tue Jul 19 18:40:41 EDT 2022 | emeto
Nitrogen is helping voids, so if you have specific parts that are prone to voids, you might start seeing more voids. Joints will probably look a little dull in comparison and this might affect your existing AOI programs.
Electronics Forum | Thu Sep 11 15:23:31 EDT 2003 | Peter L.
I have come across a rash of failed assemblies that have 0805 capacitors and resistors, bottom side glued, wave soldered and washed. Trouble shooter reported touching up the solder joints on a few areas and the boards would pass test. I had a look a
Electronics Forum | Sat Jul 16 13:53:52 EDT 2022 | yannick_herzog
Hello all, we use a reflow oven from Rehm in our SMT production. At the moment we solder under nitrogen atmosphere (approx. 500ppm). Now we want to reduce the nitrogen consumption (costs etc.). What consequences can occur here? Especially on the s
Electronics Forum | Sat Jan 08 11:12:49 EST 2000 | S. Evers
Hi all, Best Thing Since Sliced Bread? No doubt many of you have seen Phil Zarrow's "over-the-top" review in Circuits Assembly of the new Ersa scope, a device that allows viewing a really neat close up a side view of the component substrate interface
Electronics Forum | Tue Aug 14 08:19:45 EDT 2018 | buckcho
Hello, other colleagues gave you valid ideas. I found it helpful if i reduce the size of the cooling openings. I would suggest making the four big square into very small many diamonds. This would maybe decrease your voiding with 2-4 percent. Btw how
Electronics Forum | Fri Jul 20 13:50:22 EDT 2018 | vchauhan
This question is regarding stencil design: I am having voids under QFN TI P/N LMZ20502SILT. I have attached component pic. Signal pin is 18X16 mils. Center pads are 31 mil sq. Initially I had stencil done with one mil per side reduction on signal pad
Electronics Forum | Mon May 27 04:46:11 EDT 2019 | SMTA-Rogers
Dear CW, Yes, we also tested many different brands and models of solder paste, under the same stencil design and reflow profile the condition of the voids will have great difference.
Electronics Forum | Fri Nov 23 16:32:05 EST 2007 | davef
There a several things you can do to prevent the solder wicking down the hole with the current design, and that's where you should focus. Cost goes up as you go down the list, but in neither case do you need to respin the board, have solder starvatio
Electronics Forum | Sat Nov 24 15:44:28 EST 2007 | mika
Hi DaveF, I had a short look into the Nr1. IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Most interesting reading, but one thing though, I could not find any information about the oven profile. Just a picture of it. My question is of about the
