Electronics Forum: spi defect rates (Page 1 of 28)

Re: acceptable defect rates for smt process, in ppm.

Electronics Forum | Sat Jan 15 13:13:33 EST 2000 | Mark Wiegold

Steve, Basically in answer to your question, there is no real set number for defects. Defect rates will vary between products and companies. If my company was running the same product as yourself then there is no reason to suggest that the defect ra

acceptable defect rates for smt process, in ppm.

Electronics Forum | Fri Jan 14 16:48:40 EST 2000 | Steve Thomas

O.K., folks, I know this is a loaded question, but I've been asked to find the answer, sooooo: What is an acceptable defect rate in ppm for a surface mount process, assuming that each component has the potential for one defect. This would include de

Re: acceptable defect rates for smt process, in ppm.

Electronics Forum | Tue Jan 18 20:31:10 EST 2000 | WDavidson

It makes a difference what the normalizer is. We calculate solder ppm and placement ppm separately for each assembly. Solder ppm = #solder defects*1E6/(Qty boards*#solder joints per board). For us this number is easily less than 50 and sometimes

Re: acceptable defect rates for smt process, in ppm.

Electronics Forum | Sat Jan 15 16:59:47 EST 2000 | Steve Thomas

Thanks, Mark. Actually we already have an established mark. We use 500ppm (99.95%) as our acceptable level. Problem is, someone (another manufacturer) told someone else (our pres.) that THEY build to 50ppm. Soooooo, someone else told my boss that

Re: acceptable defect rates for smt process, in ppm.

Electronics Forum | Mon Jan 17 12:16:02 EST 2000 | Brian W.

My old company (CM) ran SMT to 50ppm including some very complex boards. We established the normalizer number by: #components + #solder joints. As was stated earlier, the ppm for any given product is the result of many factors. You may get differen

smt fall-out -- acceptable rates

Electronics Forum | Wed Jul 14 13:50:11 EDT 2010 | swag

I can't offer much advice on acceptible rates or #'s. From a process standpoint, most of your bridging or insufficient originates in your printer. Look into buying dedicated tooling specifically designed for the build. We use "h-towers" on all hig

un-tested assembled circuit reject rates

Electronics Forum | Tue Dec 07 13:40:25 EST 1999 | Tim

The company I represent provides electronic manufacturing services. Some of my customers ask that we ship their boards "un-tested". By un-tested I mean we build them, visually inspect them and out they go. I find that on un-tested boards, it's not

Re: un-tested assembled circuit reject rates

Electronics Forum | Tue Dec 07 14:21:41 EST 1999 | Brian W.

In my experience, the most commonly accepted theory is that 100% inspection is only 80% effective AT BEST. That means that if your inspoectors are happy, noy outside concerns, well-rested, etc, they will catch 80% of the defects. This number goes d

Re: un-tested assembled circuit reject rates

Electronics Forum | Wed Dec 08 02:07:25 EST 1999 | Scott Cook

Tim, What Brian writes is all true. However, let em put it into a sales / marketing perspective..... The REAL issue in your situation is: Who is responsible for the failures which WILL result in shipping untested product? Typically, your customer

Tombstone defect

Electronics Forum | Mon May 05 03:53:41 EDT 2003 | praveen

Do not 'ON" the nitrogen during reflow. If the pad of the chip is bigger then reduce the pad width from out side. Reduce the ramp rate at any point of the profile below 1 deg c/sec.

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