Electronics Forum | Fri Mar 06 10:30:46 EST 1998 | Ron Costa
| | | Hello everyone! | | | Does any know anything about bare board size variations? | | | Is there a spec. or tolerance? | | | I'm running small lots of boards and during the screen printing process | | | I find that I cannot paste each board perfec
Electronics Forum | Wed Jun 22 09:12:57 EDT 2005 | bsudak
Our manufacturing site has been struggling with soldering Alloy 42 TSOPs. Currently, we have to hand solder in one of our applications. Here are the particulars. Component: 54 leads, Sn plated, 400microinches +/-200. Process: Eutectic 63/37 Sn/Pb
Electronics Forum | Tue Aug 31 19:16:59 EDT 1999 | Steve Surtees
| I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average ram
Electronics Forum | Fri Jun 18 13:55:44 EDT 1999 | Earl Moon
| | Now don't everyone jump on this at once, but it seems time for me to send out copies of my not even close to being dated copy of an article about HASL. Though it was published in 1992, in Printed Circuit Fabrication Magazine, and it got rave revi
Electronics Forum | Wed Mar 03 20:20:30 EST 1999 | Earl Moon
| We have recently had problems with bare boards coming in too thick. I would like to know how to properly specify the minimum and maximum thickness using the 13949F and IPC 4101 specs. (We currently use "MATERIAL: GFN 0620 C1/C1 A2A per MIL - P - 13
Electronics Forum | Sat Jan 16 03:06:36 EST 1999 | Wirat S.
| | Our spec on voids is 30% ball diameter in the center. On the component to ball and pad to ball interface, we use 25%. To determine this spec, we asked around. I don't know of any studies that have been done to verify if this is OK | | | | Regard
Electronics Forum | Tue May 26 17:29:42 EDT 1998 | Earl Moon
| I know, I've read the "been there done that" stories about this subject, but I still profess ignorance on some aspects. | We are using NPO type dialectric caps in potted high voltage assemblies and continue to experience catastrophic vailures. U
Electronics Forum | Tue Sep 07 17:12:34 EDT 2004 | davef
No one knows what type of board you use. So, assuming you're talking a fairly standard FR4. Q1a. actually, what is max temperature and duration can a bare PCB reflow without any quality problem? A1a. We'd guess your board could take 250*C for may
Electronics Forum | Fri Jun 18 14:28:14 EDT 1999 | Scott Cook
| | Now don't everyone jump on this at once, but it seems time for me to send out copies of my not even close to being dated copy of an article about HASL. Though it was published in 1992, in Printed Circuit Fabrication Magazine, and it got rave revi
Electronics Forum | Wed Oct 25 12:24:02 EDT 2000 | Philip
Hi Chris! I hope this will help you! The CBGA uses an array of high melting point solder spheres(Sn10/Pb90) to connect its ceramic chip carrier to an epoxy glass (FR4) PCB using eutectic (Sn63/Pb37) solder joints at both ceramic and card inter
