Electronics Forum | Fri Sep 14 01:43:36 EDT 2001 | dhanashekar
please check the following also. in one of the cases we came across the second point was the problem. 1. the parallelisum of the conveyor. 2. the warpage of the board. 3. the stencil.(the differential height in the paste deposition of the two pads
Electronics Forum | Mon Jun 15 06:21:13 EDT 2020 | ameenullakhan
Hi Team, Main reason for HIP are; 1. Warpage in component or PCB : Verified the part and PCB 1.6 mm thickness no warpage found. 2. Hip was at different locations : center as well as corner : So not because of warpage of component. 3.Solder paste equ
Electronics Forum | Wed Jan 11 18:59:22 EST 2023 | agrivon
At SMT assembly level, the main HiP mitigation actions to consider should be increasing the stencil thickness/aperture sizes (typically in the 4 corners where warpage is maximal) + possibly reducing the reflow peak temperature as probably indicated i
Electronics Forum | Tue Sep 19 05:06:05 EDT 2017 | kubabel
Thank You for these hints, we´ve checked whole temp. profile (including dwelling time) and we follow all of specifications to components. Anyway we are still facing approx. once per two months issue with our customer, where only one BGA ball is nonwe
Electronics Forum | Fri Apr 08 17:23:34 EDT 2005 | KEN
Warpage factors can cause: 1. Boards can not transfer down conveyor belts or wedge at transitions. 2. May not enter into machinery due to interferences (like board clamps) 3. May fall off conveyor chain in furnace. Especially true of thin (PCMCI
Electronics Forum | Mon Nov 12 16:14:47 EST 2001 | davef
Yes!!! How can we assemble boards with 20 pitch when we allow 0.008� error to the master art? Excellent question!!! IPC-D-300G has nothing to do with assembler requirements. It is written by and for fabricators, so that they can be comfortable.
Electronics Forum | Fri Jun 29 15:41:58 EDT 2012 | dontfeedphils
I guess I would atribute it to either board stretch/warpage or someone messed up, whether it be the gerbers aren't quite right or the stencil wasn't cut exaclty as the checkplot was laid out.
Electronics Forum | Mon Nov 26 22:05:34 EST 2007 | shy
currently i'm open my stencil aperture is 80% from the land pattern. is this will cause insufficient solder at the terminal component or not? the stencil thichness is 6mil and the board run using SMT pallet which i consider there will be no option f
Electronics Forum | Tue May 21 15:00:28 EDT 2019 | emeto
Hello Greg, Here are a few questions and advises that might post an answer: 1. How thick is your current stencil and what is the part that requires that thickness? 2. Can you use a carrier to keep your board straight and avoid board warpage? May
Electronics Forum | Fri Apr 13 10:13:30 EDT 2007 | Bob R.
We had a crisis with one BGA causing huge yield losses due to this defect. Nothing we could do with the profile got rid of it. Changing paste didn't get rid of it. It was the BGA warping in reflow, caused the corners to lift up when the solder was
