Electronics Forum | Thu Feb 03 10:22:23 EST 2000 | AF ng
Dear Dave, Thank you for your reply. What I meant thermal excursion is the solder cycle. That is for the same particular point, how many time we can solder them, for FR4 boards. Thank you
Electronics Forum | Mon Feb 14 12:07:47 EST 2000 | Dave F
Leslie: Product screens and tests of prototypes and test vehicles should be tailored for the specific goal and product. I caution your use of equations and test condition information without specific use environments and design conditions. Lawyer:
Electronics Forum | Wed May 28 08:25:08 EDT 2003 | davef
That's what we do [no more than three reworks or mods]. Your "four reworks permissable" was probably based on the 55110 five thermal cycles, counting wave soldering as the first cycle. How do you plan to keep track of each of those rework actions?
Electronics Forum | Fri Nov 27 08:07:50 EST 1998 | Earl Moon
| | | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is
Electronics Forum | Mon Feb 28 12:01:30 EST 2005 | Bob R.
We use QFNs in automotive products and have done a good bit of experimenting with pad designs, paste patterns, stencil thickness, and thermal via patterns. All of them have an effect on assembly and thermal cycle reliability. There is not a yes or
Electronics Forum | Mon Jun 20 10:59:18 EDT 2005 | Jason Fullerton
Extra cooling is better (Alpha recommends -3 to -7 degC/sec) for cosmetics. Less chance of s o called 'cooling lines' that look similar to 'cold' tin-lead joints. (Seems a bit steep to me - I worry about the risk of cracking ceramic caps.) Might be
Electronics Forum | Fri May 15 09:07:12 EDT 1998 | Earl Moon
| | I hear that there is a problem with using ceramic parts that are sizeable. Apparently, there is a mismatch in the Temperature Coefficient of Expansion between the FR4 and ceramic materials which causes the soldered erminations to weaken and event
Electronics Forum | Thu Sep 14 13:34:43 EDT 2000 | Boca
Of course the others have great answers, try NOT to do it, for all of their reasons. However, had to do it in the past, OEM, custom chip, die wouldn't fit in a SM package, volume wouldn't support a second package type ...... and on and on. So we us
Electronics Forum | Thu Jun 14 23:21:30 EDT 2001 | oem boy
I am working on 0201 development for my company in the UK, and I am planning a rather extensive DOE for my reflow oven profile. I am planning on studying various ramp rates, soak times, times above liquidus, peak temps, etc... My biggest concern
Electronics Forum | Wed Dec 29 15:42:34 EST 1999 | Mike Naddra
Justin, I would be currious as to your customers application, and if the temperature delta and rate are great enough to cause solder joint failures as a function of mismatched Tce then you may want to consider that even if you are able to identify
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