Electronics Forum | Thu Sep 14 14:37:45 EDT 2000 | Serrena Carter
Does anyone know where I can find good rule of thumb information on soldering/brazing. I am most interested learning the maximum recommended CTE mismatch between two different materials that thermally cycle between 25-100C.
Electronics Forum | Wed Feb 07 18:40:39 EST 2007 | bill
What is an acceptable mismatch for smt components and pcb. We are having cracked solder joints from fatigue after repeated thermal cycling 25 deg. c to 125 deg.c.
Electronics Forum | Fri Sep 15 16:37:49 EDT 2000 | Dave F
Sounds like someone aimin� fo tha big hurt, if ya axes me. Two spots to place your lawn darts are: 1 J Hwang in "Modern Solder Technology � " states (p.354) that " � extreme CTE mismatch between silicon IC (~2) and the PCB (~16), solder connections
Electronics Forum | Fri May 15 09:07:12 EDT 1998 | Earl Moon
| | I hear that there is a problem with using ceramic parts that are sizeable. Apparently, there is a mismatch in the Temperature Coefficient of Expansion between the FR4 and ceramic materials which causes the soldered erminations to weaken and event
Electronics Forum | Wed May 06 09:16:51 EDT 1998 | justin medernach
| I hear that there is a problem with using ceramic parts that are sizeable. Apparently, there is a mismatch in the Temperature Coefficient of Expansion between the FR4 and ceramic materials which causes the soldered erminations to weaken and eventua
Electronics Forum | Wed Dec 29 15:42:34 EST 1999 | Mike Naddra
Justin, I would be currious as to your customers application, and if the temperature delta and rate are great enough to cause solder joint failures as a function of mismatched Tce then you may want to consider that even if you are able to identify
Electronics Forum | Thu Apr 16 08:01:38 EDT 2009 | kpm135
I've had some luck with longer soak. Of course that was on a board with severe thermal mismatches so I don't know if it will help your problem or not.
Electronics Forum | Sat Mar 01 08:17:40 EST 2003 | davef
You're correct that the FR4 is probably the best choise. The majority of the problems in developing your reflow recipe is going to come from the CTE mismatches in the CCBGA , CBGA and PBGA that you put on the board. The other side says given the pr
Electronics Forum | Thu Nov 26 03:59:50 EST 1998 | Chi-Ting Chen
I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is cause
Electronics Forum | Thu Nov 26 06:07:40 EST 1998 | Earl Moon
| I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is cau
