Electronics Forum | Thu Jan 07 09:44:57 EST 2010 | cbart
What material is used to cap a via? Is it the standard LPI Process/Material?
Electronics Forum | Wed Jan 27 20:11:36 EST 2010 | plerma
What material is used to cap a via? Is it the > standard LPI Process/Material? we tent vias all the time, mostly to assist with assembly and the majority of the time outgassing is not a problem. What is the purpose in your case?
Electronics Forum | Mon Jan 11 14:48:44 EST 2010 | davef
SR1000 is commonly used for tenting. Search the fine SMTnet Archives on : tenting Someone gave us this note. We have lost their name. It seems to be good advice. If Liquid Photo Image (LPI) solder mask is required, do not tent via holes. Tenting
Electronics Forum | Fri Nov 03 07:28:27 EST 2006 | davef
Via filling methods are: * Tenting * Plugging * Capping * Flooding Tented Via. A via covered with dry film soldermask; the via is not filled. When tenting from both sides there may be issues with trapped air that expands during mass soldering. Plug
Electronics Forum | Tue Oct 15 15:16:34 EDT 2002 | Abelardo Rodriguez Santana
We run into that issue all the time. If a corrective action must be done right away. Place Kapton tape on the bottom side of the board to cap off the via. If you have room to place tape if not use pink lady or something to plug the via. And weathe
Electronics Forum | Tue Feb 01 04:11:58 EST 2000 | emmanuel
I am to assembly a power SO on the top side of a double side board. My designer has implemented a lot of thermal vias in the heat sink pad of this component. The problem is that i need to prevent the solder cream from polluting the bottom side of the
Electronics Forum | Tue Feb 01 21:53:06 EST 2000 | Dave F
Emmanuel: You have choices to prevent the solder paste from flowing to the second side during reflow: 1 Have your board fabricator plug the vias. 2 Put a temporary solder mask on the secondary side vias. 3 Have your designer relay-out the vias unde
Electronics Forum | Thu Aug 15 15:58:12 EDT 2002 | robertnguyen
To whom this may concern, I recently ran into the problem with vias on pads of BGA when place BGA and reflow gas trap on vias escape and result in ball having void greater than 50% of BGA diameter. The BGA pad is measured at 20 mils and the vias mea
Electronics Forum | Thu Oct 06 21:46:32 EDT 2016 | piyakorn
am worrying on a hight temp that will affect to others components mounted on board or not such ICs.. Thank you davef -
Electronics Forum | Wed Oct 05 04:32:49 EDT 2016 | piyakorn
Rinse IPA 5 Min --> Treathment/soak IPA50%+SILENT50% 5Min --> Baking 60C/30Min --> Parylene coating (around 8Hr in chamber) --> Found defect spot. We have simulated and ensure board drying before parylene that still have spots. Need help - Thank y
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