Electronics Forum | Fri Jul 19 13:09:55 EDT 2019 | edhare
Hi, Are you referring to the condition illustrated here? ... https://www.semlab.com/qfn-solder-fillets In this case, the solder was wicked down an attached un-filled PTH via. Ed Hare SEM Lab, Inc.
Electronics Forum | Thu Jun 28 09:57:50 EDT 2012 | mosborne1
blow holes and via holes are almost always caused by moisture and in PTH they could be moisture and improper drilled holes. If you are seeing solder balls next to the parts than I would say you have a reflow profile problem. Are you using any kind of
Electronics Forum | Thu Jun 28 17:05:46 EDT 2012 | davef
Here’s what we seem to know: * There’s a problem with voiding in the solder connections of SMT capacitors * A void is an open area caused by air or process fluid that is trapped within a solder connection * Voids are an allowable condition as long as
Electronics Forum | Fri Apr 27 10:55:54 EDT 2007 | Brett
Pete, is there a probe-style that will accomodate a via that's filled, but a little concave (inward) fillet? The ICT personnel complains about this scenario too. I'm not an ICT person, but I do know that there are pogo pins that have a crown (for t
Electronics Forum | Fri Dec 22 11:32:56 EST 2006 | realchunks
We generaly reduce 25% and get great heat sink capability. Mind you that we do not perferate the pad with vias as recommended. Our toe ends are not plated, so getting any toe fillet is impossible.
Electronics Forum | Fri Apr 27 08:44:08 EDT 2007 | Brett
For those of you who use via holes as test points, and the via holes must be filled at the wave, is it necessary to have a "dome" on every single test point, or is it sufficient to have the via "filled" with solder? The ICT preson here insists that
Electronics Forum | Thu Feb 03 13:23:30 EST 2005 | caldon
Hi Steve- We have a Glenbrook system and are pretty pleased with it....as far a value vs. cost it works great. I did have an issue with a Soic with a ground plane in the center...yes SOIC!!! The Ground plane was a heat sync that had vias for thermal
Electronics Forum | Tue Dec 17 11:01:24 EST 2002 | Tim Marc
Hello all, One of our PCB manufacturers coated a through hole connecters vias with solder mask. The only IPC references that comes close to describing this problem is 2.9.2 Registration to holes, and subsequent specification 6.3.1 PTH � Vertical fil
Electronics Forum | Thu May 01 09:26:53 EDT 2008 | scottp
Voiding was also the issue I had. I could reduce them substantially by pre-baking the boards, but that's obviously not desirable. Hopefully the chemists have come up with a solution. I extruded some pretty cool looking solder shorts through the vo
Electronics Forum | Thu Nov 25 21:43:49 EST 1999 | cklau
Via is normally a plated thru holes in (0.63 to 1.0 mm (0.025" to 0.040") diameter lands , which unless properly treated they must be located away from the component lands to prevent the solder migration off the component land during reflow soldering
