Electronics Forum | Tue Nov 20 06:02:11 EST 2007 | mattkehoe
http://www.sipad.com/sipad_vip.htm mk
Electronics Forum | Fri Nov 23 17:33:11 EST 2007 | mika
English => Swenglish, is not so good... Ds.
Electronics Forum | Fri Nov 09 10:15:27 EST 2007 | devajj
Of course if you are an OEM you could go back to your design engineers and tell them via's in SMD pads is unacceptable. Put that in your DFM design guidelines. If you are an EMS provider you can also influence your customer by explaining the impa
Electronics Forum | Tue Nov 13 09:36:18 EST 2007 | rgduval
From a manufacturing standpoint, this isn't very nice. Vias will tend to wick solder away from the pad, resulting in insuficient solder joints, which require touch-up. The amount of times any solder joint is reheated should be minimized, as extra h
Electronics Forum | Fri Apr 12 17:22:47 EDT 2002 | davef
First, splitting hairs on parlance. * Conformal Coating. A thin electrically nonconductive protective coating that conforms to the configuration of the covered assembly to provide environmental and mechanical protection. * Solder Mask. Coating mate
Electronics Forum | Sat Nov 24 15:44:28 EST 2007 | mika
Hi DaveF, I had a short look into the Nr1. IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Most interesting reading, but one thing though, I could not find any information about the oven profile. Just a picture of it. My question is of about the
Electronics Forum | Wed Mar 15 01:20:08 EST 2000 | Dreamsniper
Do we really need not to locate vias underneath discrete components on a PCB that will be wave soldered after reflow even though we are using no clean process on our wave solder ? What are the possible cause and effect when locating Vias under discre
Electronics Forum | Wed Mar 15 21:57:16 EST 2000 | Dreamsniper
DaveF, Thanks to all the support you were providing me. Appreciate all the help. Armin
Electronics Forum | Wed Mar 15 20:28:17 EST 2000 | Dave F
Armin: Locating vias within the courtyard of components is bad practice. Concerns are: * Poor solder paste print quality, caused by the via preventing good stencil gasketing. * Poor component reflow, caused by the via holding the component out o
Electronics Forum | Tue Nov 23 23:42:34 EST 1999 | armin
Is there a Standard/Guidelines that (or which IPC guidelines) defines the pad edge-pad edge clearance for Various via hole and component land sizes. Also defining why Vias shouldn't be placed under discrete components.
