Electronics Forum | Thu Aug 15 15:58:12 EDT 2002 | robertnguyen
To whom this may concern, I recently ran into the problem with vias on pads of BGA when place BGA and reflow gas trap on vias escape and result in ball having void greater than 50% of BGA diameter. The BGA pad is measured at 20 mils and the vias mea
Electronics Forum | Fri Aug 16 09:59:49 EDT 2002 | dason_c
We baked the board first and print 2 mil water soluble paste at the BGA location and reflow. Wash and baked before the production run.
Electronics Forum | Fri Aug 16 10:00:03 EDT 2002 | davef
You have a very bad situation. It�s tough for the gas, flux material, er whatever to escape when the BGA is sitting on top of it and the blind via is blocking it from the other side. Obviously the vias should have been: * Placed on the edge of the
Electronics Forum | Thu Jun 02 08:42:06 EDT 2016 | emeto
Several important things to watch. 1. More paste can result in more voiding(I usually shoot for 50-65% coverage) 2. Make a different grid(windowpane) for you pad - try with more smaller windows 3. Try both ramp to spike or Soak profiles and see whic
Electronics Forum | Thu Jun 02 22:40:13 EDT 2016 | slouis2014
Hi, yes have a few experiments initially i tried to increase the solder volume but component pin have insufficient solder. 1. The solder coverage do you calculate it by solder volume or solder area. 2. if i would achieve as you recommend 50-60 % woul
Electronics Forum | Mon Sep 30 09:26:04 EDT 2002 | itempea
Russ, first step would be to get IPC-7095 on BGAs. A few notes: There can be voids in solder balls, or at the solder joints to the BGA, or at the solder joints to the PCB. Various sources or reasons can be responsible for these voids. Voids can be
Electronics Forum | Fri Jun 20 03:47:24 EDT 2008 | philip
Hi all, any good recommendation for PbF paste application to reduce voids underneath the QFN thermal pad (stencil thickenss? opening? via hole? reflow profile etc)? We have tried few stencil opening design but no significant improvement as seen. Ther
Electronics Forum | Thu Dec 13 20:54:23 EST 2001 | davef
There is neither �nominal thickness� nor �is there a set maximum� for via masking. We use some of our vias as test pads. So, as you�d expect, we get rabid when we get mask bleed onto these pads. IPC-6012 - Qualification & Performance For Rigid Pri
Electronics Forum | Wed Mar 24 11:09:44 EDT 2010 | rajeshwara
Hello Sir I faced the same problem for QFP in DTH product in India. IPC stated that void should not be more than 25% of solder joint. But this type of void definatly create problem during functional test. Please check the folloeing point... 1.Check t
Electronics Forum | Sat Mar 27 08:15:02 EST 2004 | davef
Via in pad is a designer's dream and an assembler's nightmare. Search the fine SMTnet Archives for previous discussions to get started. VIP, via-in-pad, or whatever tend to promote voiding within the via and certainly partially starved solder conne
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